https://sunhong.dev/en/ A technical blog on AI, hardware and development en Mon, 14 Sep 2026 17:10:29 GMT https://sunhong.dev/en/post/federated-learning-fedprox-scaffold/ https://sunhong.dev/en/post/federated-learning-fedprox-scaffold/ I compared the performance of the FedProx and SCAFFOLD federated learning algorithms on non-IID data. Experiments used the AG News text classification dataset and a GRU model, and I analyzed each algorithm's convergence behavior. Tue, 20 Jan 2026 17:11:41 GMT Sunhong Federated Learning FedProx SCAFFOLD GRU NLP PyTorch wandb https://sunhong.dev/en/post/nell-knowledge-graph-gcn/ https://sunhong.dev/en/post/nell-knowledge-graph-gcn/ I performed node classification on the NELL knowledge graph dataset with a GCN (Graph Convolutional Network). I implemented the model in PyTorch Geometric and reached 97.86% test accuracy on 65,755 nodes and 186 classes. Tue, 20 Jan 2026 17:11:41 GMT Sunhong GNN GCN NELL Knowledge Graph Node Classification PyTorch Geometric https://sunhong.dev/en/post/guessing-game-robot-arm-hri/ https://sunhong.dev/en/post/guessing-game-robot-arm-hri/ I helped develop a guessing game system based on human-robot interaction that combines YOLO object detection with a VLM (vision-language model). We built a game in which the robot arm infers and points to an object from the user's clues. Tue, 20 Jan 2026 17:09:23 GMT Sunhong HRI Robot Arm YOLO VLM LLaMA InternVL UNIST https://sunhong.dev/en/post/rectilinear-steiner-tree-routing/ https://sunhong.dev/en/post/rectilinear-steiner-tree-routing/ I implemented a Dijkstra-based Rectilinear Steiner Minimum Tree (RSMT) algorithm for routing optimization in VLSI design. It minimizes total wirelength by selecting Steiner candidate points from the Hanan grid and optimizing iteratively. Tue, 20 Jan 2026 17:09:21 GMT Sunhong VLSI RSMT Steiner Tree Dijkstra CAD Routing https://sunhong.dev/en/post/lab-website-wordpress/ https://sunhong.dev/en/post/lab-website-wordpress/ I built the website of the Intelligent Systems Lab at Yonsei University on WordPress, implementing research area pages, member management, a publication archive, and news/gallery features. Tue, 20 Jan 2026 17:08:58 GMT Sunhong WordPress Website Lab Homepage PHP CMS https://sunhong.dev/en/post/django-tech-blog/ https://sunhong.dev/en/post/django-tech-blog/ I built a personal tech blog with Django and plain JavaScript/CSS. I implemented Markdown-based writing, hierarchical categories, AI features (Gemini), and SEO optimization myself. Tue, 20 Jan 2026 17:08:56 GMT Sunhong Django Blog Python PostgreSQL Full-Stack https://sunhong.dev/en/post/dqn-double-dqn-per/ https://sunhong.dev/en/post/dqn-double-dqn-per/ Compares three reinforcement learning algorithms, DQN, Double DQN, and PER, in the CartPole, Acrobot, and MountainCar environments, and analyzes the characteristics and limits of each. Sun, 18 Jan 2026 18:45:59 GMT Sunhong Reinforcement Learning DQN Deep Learning PyTorch https://sunhong.dev/en/post/arduino-fire-extinguisher/ https://sunhong.dev/en/post/arduino-fire-extinguisher/ KURUNG, an Arduino auto fire extinguisher entered in Sungkyunkwan University's 2021 Creative Capstone Design Competition. We built a low-cost IoT device that judges flame, smoke, and temperature sensors together to detect kitchen fires early, sprays extinguishing agent, and alerts a smartphone. Wed, 17 Jan 2024 00:00:00 GMT Sunhong Hardware arduino https://sunhong.dev/en/post/radix-8-booth-multiplier/ https://sunhong.dev/en/post/radix-8-booth-multiplier/ I designed a multiplier in Verilog that combines Radix-8 Booth encoding with TDM. This post covers how the Booth algorithm works, the number of partial products and hardware trade-offs at each radix, the Radix-8 encoding table, implementation and verification, and lessons learned. Wed, 27 Dec 2023 00:00:00 GMT Sunhong verilog vivado https://sunhong.dev/en/post/radix-4-booth-multiplier/ https://sunhong.dev/en/post/radix-4-booth-multiplier/ I designed a radix-4 multiplier in Verilog that cuts the number of partial products with Booth encoding and compresses them with TDM. Covers the Booth encoder and selector, partial product generation, the carry save adder, the Kogge-Stone final adder, and the accuracy verification waveforms. Wed, 27 Dec 2023 00:00:00 GMT Sunhong verilog vivado https://sunhong.dev/en/post/cortex-m0-soc-robot-control/ https://sunhong.dev/en/post/cortex-m0-soc-robot-control/ Designed an SoC on a Basys3 board that combines a Cortex-M0 with AHB-Lite peripherals. Covers the HW and SW of a multifunction system that controls a small robot over UART and runs an up counter, a stopwatch, a random number generator/multiplier, and an adder/subtractor, along with the results. Wed, 27 Dec 2023 00:00:00 GMT Sunhong verilog vivado https://sunhong.dev/en/post/differential-amplifier/ https://sunhong.dev/en/post/differential-amplifier/ Designed a differential-input, single-ended-output amplifier with over 60 dB of gain in SIMetrix. The first stage is a differential amplifier biased with a current mirror and the second stage is a source-coupled amplifier, and I checked the output waveform for a 1 mV input at 5 V and 100 uA. Wed, 13 Dec 2023 00:00:00 GMT Sunhong circuit https://sunhong.dev/en/post/verilog-slot-machine-lfsr/ https://sunhong.dev/en/post/verilog-slot-machine-lfsr/ I designed a slot machine for the Basys3 board in Verilog. A timer seeds an LFSR to produce three BCD random numbers, and the output is 2x, 5x, or 10x the input depending on how many digits match. Covers the block diagram, sub-block definitions, simulation waveforms, and discussion. Wed, 13 Dec 2023 00:00:00 GMT Sunhong verilog vivado https://sunhong.dev/en/post/wallace-tree-multiplier/ https://sunhong.dev/en/post/wallace-tree-multiplier/ I designed an 8-bit parallel multiplier in Verilog using the Wallace tree structure, which reduces partial sums stage by stage with half adders and full adders. Covers the computation that produces the 16-bit product, the design flow, the testbench, and the full code. Wed, 13 Dec 2023 00:00:00 GMT Sunhong verilog vivado https://sunhong.dev/en/post/risc-v-5-stage-pipeline/ https://sunhong.dev/en/post/risc-v-5-stage-pipeline/ I designed a 5-stage pipelined RISC-V processor in Verilog that supports the full RV32I instruction set. This post covers resolving data and control hazards with a hazard detection unit and a forwarding unit, and verifying the design with iverilog and GTKWave waveforms. Wed, 13 Dec 2023 00:00:00 GMT Sunhong verilog C https://sunhong.dev/en/post/breadboard-computer-74ls/ https://sunhong.dev/en/post/breadboard-computer-74ls/ Following Ben Eater's design, I built an 8-bit computer on breadboards using only 74LS-series TTL chips. A record of learning the CPU's instruction execution cycle by wiring the clock, registers, ALU, RAM, program counter, and control unit by hand. Wed, 13 Dec 2023 00:00:00 GMT Sunhong Hardware https://sunhong.dev/en/post/android-restaurant-picker-app/ https://sunhong.dev/en/post/android-restaurant-picker-app/ Mechu, an Android app built to answer "what should I eat today?" It finds restaurants near you with the Naver Local Search API, picks one at random with a single button, and shows it on Kakao Map. Covers location permissions, animation, category filters, and the release process. Wed, 13 Dec 2023 00:00:00 GMT Sunhong kotlin android_studio https://sunhong.dev/en/post/github-pages-jekyll-blog/ https://sunhong.dev/en/post/github-pages-jekyll-blog/ A record of building my first blog with GitHub Pages + Jekyll. This post walks through setting up a GitHub Blog, a rite of passage for many developers. Why a GitHub Blog: to run a blog as a developer portfolio, the following conditions matter: - Tracking post history with version control... Wed, 13 Dec 2023 00:00:00 GMT Sunhong HTML CSS JS GIT Jekyll SASS https://sunhong.dev/en/post/dc-motor-pid-control/ https://sunhong.dev/en/post/dc-motor-pid-control/ I designed a position controller for a DC servo motor in MATLAB. Under the requirements of a damping ratio of 0.4–0.7, a settling time under 1/30 s, and a phase margin of at least 40 degrees, I found the PID gains with the root locus, checked that the requirements were met and searched for the optimum, and wrote up my reflections. Wed, 13 Dec 2023 00:00:00 GMT Sunhong matlab https://sunhong.dev/en/post/power-generation-transmission-planning/ https://sunhong.dev/en/post/power-generation-transmission-planning/ A generation and transmission planning project from a power systems engineering course. It models new power plants and transmission expansion to meet long-term demand growth as a cost-minimization problem, and covers the constraints, power flow calculation, MILP optimization, and scenario analysis. Wed, 13 Dec 2023 00:00:00 GMT Sunhong Hardware