RISC-V 5-Stage Pipeline: Forwarding and Stall Conditions, Handling x0
Part 17 of the RISC-V series. I ran the same programs on a 5-stage pipeline model, matched them against QEMU, and measured CPI: 1.37 with forwarding, 1.83 without. Dropping the rd≠0 condition made a program using the HINT ntl.all write 0x80000000 instead of 0.
Sunhong'sSystem Blog
RISC-V