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RISC-VRISC-V Branches and Jumps: Resolve Stage, JAL/JALR, Return-Address Stack Hints
Part 18 of the RISC-V series. I added the branch resolve stage, JAL redirect in ID, BTFN static prediction, and a RAS that follows the hints in spec section 2.5 to a pipeline model and compared them. CPI dropped from 1.368 to 1.227, and an 8-entry RAS predicted 98.3% of fib's returns.
RISC-VRISC-V 5-Stage Pipeline: Forwarding and Stall Conditions, Handling x0
Part 17 of the RISC-V series. I ran the same programs on a 5-stage pipeline model, matched them against QEMU, and measured CPI: 1.37 with forwarding, 1.83 without. Dropping the rd≠0 condition made a program using the HINT ntl.all write 0x80000000 instead of 0.
RISC-VThe Immediate Generator and a RISC-V Single-Cycle Datapath
Part 16 of the RISC-V series. I turned the selector table from Part 2 into an immediate generator circuit and assembled a single-cycle datapath. Running 5 programs and 1,076,364 instructions matched QEMU on every pc trace and register, and 20.0% of instructions were branches (58.5% of them taken).
RISC-VRISC-V Decoder Design: Decode Tables, Formats, and Illegal Instructions
Part 15 of the RISC-V series. Fills in the RV32I decode table down to the control signals and defines five illegal instruction conditions, then checks it against GNU objdump on 174,608 words. 165,923 matched, and all 8,685 mismatches were explained by four causes.
RISC-VThe Memory Model: RVWMO, What FENCE Means, and Ztso
Part 9 of the RISC-V series. Covers preserved program order in the RVWMO memory model, fence pred/succ, aq/rl, and Ztso. I enumerated 7 litmus tests under SC, TSO, and RVWMO to count whether MP, SB, and LB are allowed, and compared GCC's C11 atomic mappings under RVWMO and Ztso.
RISC-VThe A Extension: LR/SC, AMOs, and aq/rl
Part 8 of the RISC-V series. I checked the A extension's LR/SC reservations and failure conditions, the nine AMOs, and the aq/rl bits on QEMU. With 8 harts racing on a counter, plain increments kept only 22% while every atomic method was exact, and I found that QEMU lets sc succeed after another hart re-stores the same value.
RISC-VThe M Extension: Multiply, Divide, and the Rules for Divide-by-Zero and Overflow
Part 7 of the RISC-V series. Covers the 13 multiply and divide instructions of the M extension and the defined results for divide-by-zero and overflow (no exceptions), then runs 1,948 boundary cases on QEMU and confirms they all match a reference model. Without M, each multiply costs 86 extra instructions.
RISC-VFENCE.I and Self-Modifying Code: What the Instruction Side Must Honor
Part 22 of the RISC-V series. Covers FENCE.I and self-modifying code. Without fence.i, QEMU ran the new code when it was written elsewhere but the old code inside the block being executed. Running 16 combinations on an instruction-set model, I identified the minimal FENCE.I implementation for each core organization.
RISC-VC Extension: Decompressor, 16-Bit Fetch, and Misaligned 32-Bit Instructions
Part 21 of the RISC-V series. I built the C extension's decompressor and fetch buffer in Python and checked all 49,152 16-bit values and a real rv32imc program against objdump. 36.7% of executed instructions spanned two words, and the fetch buffer cut word reads from 33,771 to 23,903.
RISC-VImplementing the A Extension: Reservations, Where AMOs Run, aq/rl, FENCE
Part 20 of the RISC-V series. I compared LR/SC reservation sets, AMO atomicity, and aq/rl and FENCE implementations with a two-hart model. If reservations aren't cleared on another hart's store, the counter drops to 69.6%, and QEMU let SC succeed in all 20 runs of an ABA test.
RISC-VImplementing the M Extension: Multiply/Divide Units and Divide-by-Zero
Part 19 of the RISC-V series. I implemented the M extension's multiplier and divider as bit-exact Python models. A single 33-bit multiplier handles all three mulh variants, with zero mismatches across 300,000 pairs and 648 QEMU results, and I found a trap when dividing a negative number by zero (5,039 mismatches).
RISC-VSmall Extensions: Zicsr, Zifencei, Zicntr·Zihpm, B (Zba·Zbb·Zbs), Zicond, Zicbom
Part 12 of the RISC-V series. I check in QEMU the rule by which CSR instructions decide whether to read or write based on whether rd and rs1 are x0, and run the B and Zicond instructions over 2,772 combinations on RV32 and 3,720 on RV64, all matching a reference model. Enabling B shrank the code by 6.6–9.0%.
RISC-VThe C Extension: Compressed Formats and Their 32-bit Equivalents
Part 11 of the RISC-V series. Covers the nine 16-bit formats of the C extension and their 32-bit equivalents, then checks a hand-written decompressor against objdump for all 49,152 16-bit values. In real code, 51–69% of instructions became 16-bit, shrinking code by 26–34%.
RISC-VF and D Extensions: FP Registers, Rounding, fcsr Flags, NaN Boxing
Part 10 of the RISC-V series. I ran 229 instructions on QEMU covering the F and D extensions' rounding modes and exception flags, the canonical NaN, NaN boxing, and saturation rules for out-of-range integer conversion, and confirmed that all of them matched an exact-fraction reference model.
RISC-VV Extension 2: Masks, Load/Store Types, Reductions, Permutes, Tail/Mask Agnostic
Part 14 of the RISC-V series. I ran v0 masks, the four kinds of loads and stores, a first-fault strlen, reductions and permutations, and ta/ma in QEMU. Four kernels matched Python on all 78 items, and at VLEN 1024 they executed 4–7% as many instructions as scalar code.
RISC-VV Extension 1: VLEN, SEW, LMUL, vsetvli, and Vector-Length-Agnostic Code
Part 13 of the RISC-V series. Covers vector registers, VLEN, SEW, and LMUL, and the rules by which vsetvli sets vl. Running the same machine code on QEMU at VLEN 128 to 1024, a 100-element add looped 25, 13, 7, and 4 times and executed 313 to 61 instructions (813 for scalar).
RISC-VAssembly and the ABI: Registers, Calling Convention, Stack Frames, ELF
Part 6 of the RISC-V series. I follow the psABI calling convention and stack frame through real C functions. The work() frame was 80 bytes, and arguments from the 9th onward went on the stack. I checked argument locations per ABI and relocations, and linker relaxation shrank .text from 800 bytes to 712 bytes.
RISC-VRV64I: W Instructions, Sign-Extension Rules, and What Differs from 32-Bit
Part 5 of the RISC-V series. I checked RV64I's W instructions and sign-extension rules on QEMU. 0x7fffffff+1 became 0xffffffff80000000 with addw, and 64-bit constants took an average of 7.887 instructions with li. I also look at why utoa10 from part 1 grew.
RISC-VRV32I 3: Branches, Jumps, Loads/Stores and Alignment, FENCE, ECALL/EBREAK
Part 4 of the RISC-V series. I ran the six branches, jal/jalr, load sign extension, misaligned accesses, and fence/ecall/ebreak on QEMU. jalr turned 0x80000021 into 0x80000020, and all 56 results matched a reference model.
RISC-VRV32I 2: Integer Ops, Compares, Shifts, and Building Constants with lui/auipc
Part 3 of the RISC-V series. Checks RV32I integer arithmetic, compares, shifts, and flagless overflow handling on QEMU with 15 edge cases, then examines the +1 correction for building 32-bit constants and addresses with lui and auipc through 1 million random trials.
RISC-VRV32I 1: Registers, Six Instruction Formats, and Why Immediates Are Scrambled
Part 2 of the RISC-V series. Looks at RV32I's registers and six instruction formats, and explains why the immediate bits are scrambled by counting multiplexer inputs in the immediate generator (70 vs. 98). A hand-written encoder and decoder were checked against GNU as on 5,000 instructions.
RISC-VRISC-V Overview: The Spec, ISA Names, and What Extensions Do to Code
Part 1 of the RISC-V series. Covers the design principles of a modular ISA, how the specification is split into two volumes (Unprivileged and Privileged), and how to read names like rv64gc, then compiles the same C functions under different extension combinations and measures the code size dropping from 972 bytes to 402 bytes.
AI NoteNeural Network Basics: From the Perceptron to Multilayer Networks
Part 1 of AI Note. Starting from a single neuron's weighted sum and activation, we follow why the perceptron cannot solve XOR and how stacking layers solves it, softmax and cross-entropy loss, and gradient descent under different learning rates, all with numeric examples worked out by hand.
AI NoteBackpropagation: Gradients via the Chain Rule and MNIST in NumPy
Part 2 of AI Note. We follow backpropagation through the chain rule and computational graphs, starting from numeric examples, derive the gradients of a two-layer network in matrix form, and implement it from scratch in NumPy to reach 97.7% on MNIST. We also measure why minibatches are fast.
AI ProjectFederated Learning in Distributed Settings: Comparing FedProx and SCAFFOLD
I compared the performance of the FedProx and SCAFFOLD federated learning algorithms on non-IID data. Experiments used the AG News text classification dataset and a GRU model, and I analyzed each algorithm's convergence behavior.
AI ProjectNode Classification on a Knowledge Graph: Analyzing NELL with a GCN
I performed node classification on the NELL knowledge graph dataset with a GCN (Graph Convolutional Network). I implemented the model in PyTorch Geometric and reached 97.86% test accuracy on 65,755 nodes and 186 classes.
Other ProjectBuilding a Guessing Game System Based on Human-Robot Interaction
I helped develop a guessing game system based on human-robot interaction that combines YOLO object detection with a VLM (vision-language model). We built a game in which the robot arm infers and points to an object from the user's clues.
Other ProjectDesigning a Rectilinear Steiner Tree Algorithm for VLSI Routing
I implemented a Dijkstra-based Rectilinear Steiner Minimum Tree (RSMT) algorithm for routing optimization in VLSI design. It minimizes total wirelength by selecting Steiner candidate points from the Hanan grid and optimizing iteratively.
Web & App ProjectBuilding a Lab Website: An Academic Site on WordPress
I built the website of the Intelligent Systems Lab at Yonsei University on WordPress, implementing research area pages, member management, a publication archive, and news/gallery features.
Web & App ProjectBuilding a Personal Tech Blog: A Full-Stack Web Application on Django
I built a personal tech blog with Django and plain JavaScript/CSS. I implemented Markdown-based writing, hierarchical categories, AI features (Gemini), and SEO optimization myself.
AI ProjectImplementing Deep RL Algorithms: Comparing DQN, Double DQN, and PER
Compares three reinforcement learning algorithms, DQN, Double DQN, and PER, in the CartPole, Acrobot, and MountainCar environments, and analyzes the characteristics and limits of each.
Embedded NoteIntro to ARM Embedded Systems: ARM vs. Thumb Instruction Sets
Notes from an introduction to ARM embedded systems. Covers what an embedded system is and why ARM is used there, and compares the data sizes and characteristics of the 16-bit Thumb instructions introduced in ARMv4 with the 32-bit ARM instructions.
SoC NoteARM Cortex-M0 Architecture: Register Set, Operating Modes, Memory Map
Notes on the Cortex-M0, an ARMv6-M core for ultra-low-power MCUs. Covers its features and structure, register set, operating modes, memory map, exceptions and interrupts, the Thumb instruction set, the 3-stage pipeline, SysTick, and a comparison with the Cortex-M3 and M4.
SoC NoteSoC Design Frameworks and the Design Productivity Gap
Notes on the SoC design flow. Covers the design productivity gap, where design productivity fails to keep up with process advances, and its remedies (abstraction, EDA automation, IP reuse), an ARM-based SoC example, a comparison of SoC, MCU, and CPU, and Apple SoCs with their die sizes.
SoC NoteSoC Programming in C: Controlling Memory-Mapped I/O Registers
Notes on programming an SoC in C. Covers memory-mapped I/O and volatile, struct-based register access, setting, clearing, toggling, and checking bits, multi-bit fields, the startup sequence, linker scripts, CMSIS, and interrupt handlers.
SoC NoteClassifying the ARM Thumb Instruction Set: Data Processing Instructions
Notes classifying the Cortex-M0 Thumb instruction set by type. Covers the syntax and encoding of register, immediate, logical, shift, and multiply data processing instructions; basic, offset, multiple, and PC-relative loads and stores; and branch instructions.
SoC NoteAMBA 3 AHB-Lite Bus Architecture: Signals and Transaction Behavior
Notes on AMBA 3 AHB-Lite, the standard system bus for Cortex-M0 and M3. Covers the single-master structure, master and slave signals, pipelined transactions and wait states, burst transfers and HTRANS, address decoding, and the AHB-APB bridge.
SoC NoteProcessor vs. Core: Instruction Stages and Layers of Abstraction
Notes on processor concepts and design. Covers the instruction processing stages, the abstraction layers from high-level languages down to machine code, the difference between a core and a processor, the processor design flow, the ARM Cortex family, design trade-offs, and a walkthrough of executing an ADD instruction.
SoC NoteComparing Chip Design Methodologies: Full-Custom, Standard-Cell, PLD
Notes on the semiconductor circuit design process and SoC design methodologies. Covers the steps from specification through layout, verification, and fabrication, a comparison of full-custom, standard-cell, and PLD approaches, and integrating internal vs. external IP and hard vs. soft IP.
SoC NoteCortex-M NVIC Interrupt Handling: Vector Table and Exception Priority
Notes on interrupt handling in the Cortex-M. Covers the difference between interrupts and exceptions, vectored and nested interrupts in the NVIC, the vector table and handling sequence, exception priority and preemption, tail-chaining and late arrival, and PRIMASK, FAULTMASK, and BASEPRI masking.
Microprocessor NoteCrossbar Bus Architecture: From Shared Bus to Full Matrix
Notes on the crossbar bus that connects multiple masters and slaves. Covers the evolution from shared bus to hierarchical bus to full matrix, the PL301 structure and arbitration schemes, pipelined and burst transfers, QoS, scaling to NoC, and clock domain crossing.
Microprocessor NoteAMBA APB Protocol: Signals and Read/Write Transfer Timing
Notes on the AMBA 3 APB protocol. Covers the characteristics and signals of this bus for low-speed peripherals, read and write transfer timing with and without wait states, the APB slave state machine, the AHB-APB bridge, and a comparison of APB and AHB.
Microprocessor NoteDigital Adder Design: Half/Full Adders and Ripple Carry Adder Delay
Notes on digital adder architectures. Covers half and full adders with propagate and generate, transistor-level design, and ripple carry adder delay, through carry lookahead, carry skip and carry select, and Brent-Kung and Kogge-Stone adders.
Microprocessor NoteHow CMOS Transistors Work: From the PN Junction to nMOS/pMOS
Notes on CMOS fundamentals. Covers ICs and VLSI, silicon and the PN junction, nMOS and pMOS transistor operation and the switch model, the CMOS inverter and compound gates such as NAND and NOR, why CMOS saves power, and the process cross-section.
Microprocessor NoteDatapath Functional Units: Barrel Shifters, Comparators, Multipliers
Notes on the functional units of a processor datapath. Covers the structure and area/delay characteristics of barrel shifters, equality and magnitude comparators, array multipliers and Booth encoding, Wallace and Dadda trees, and restoring and non-restoring dividers.
Computer Architecture NoteComputer Architecture Basics: ISA, Abstraction Layers, and Performance
Notes on the introduction to a computer architecture course. Covers abstract data types (ADTs) with a stack example, the instruction set architecture (ISA), Hennessy and Patterson's engineering methodology and its two golden rules, and performance evaluation methods and design techniques.
Computer Architecture NoteHow Virtual Memory Works: Paging and Virtual-to-Physical Translation
Notes on how virtual memory works. Covers paging, which splits the virtual address space into pages, translation from virtual to physical addresses, page table organization and the PTBR, the TLB, and the pros and cons of demand paging.
Computer Architecture NoteMemory Hierarchy and Caches: The Memory Wall and Four Cache Design Questions
Notes on the memory hierarchy and caches. Covers the memory wall and temporal and spatial locality, hierarchy terminology, the four questions of cache design (placement, identification, replacement, writes), a direct-mapped cache example, and how block size relates to miss rate.
Computer Architecture NotePipelining and Hazards: Analyzing the 5-Stage MIPS Pipeline
Notes on pipelining principles using the 5-stage MIPS pipeline. Covers a performance comparison with sequential execution, structural, data, and control hazards with stalls and bubbles, the load-use hazard, a worked CPI example, and superpipelining and superscalar designs.
Computer Architecture NoteMultiprocessors and Shared-Memory Sync: Critical Sections, Producer-Consumer
Notes on multiprocessor architecture. Covers UMA and NUMA shared memory, a sum reduction example, the producer-consumer and critical-section problems, Test-and-Set mutual exclusion and optimized synchronization, message passing and clusters, and interconnect structures.
Computer Architecture NoteStorage and I/O System Architecture: I/O Buses and Reliability (MTTF)
Notes on computer I/O systems. Covers I/O bus connections and per-device data rates, the reliability metrics MTTF and MTTR and how to improve them, I/O register mapping, polling and interrupts and how they differ from exceptions, DMA, and RAID configurations.
Hardware ProjectBuilding an Arduino Auto Fire Extinguisher: Flame, Smoke, Heat Sensing + IoT
KURUNG, an Arduino auto fire extinguisher entered in Sungkyunkwan University's 2021 Creative Capstone Design Competition. We built a low-cost IoT device that judges flame, smoke, and temperature sensors together to detect kitchen fires early, sprays extinguishing agent, and alerts a smartphone.
Hardware ProjectRadix-8 Booth Multiplier: Encoding Table and TDM Trade-offs (Verilog)
I designed a multiplier in Verilog that combines Radix-8 Booth encoding with TDM. This post covers how the Booth algorithm works, the number of partial products and hardware trade-offs at each radix, the Radix-8 encoding table, implementation and verification, and lessons learned.
Hardware ProjectRadix-4 Booth Multiplier: Partial Product Reduction with TDM (Verilog)
I designed a radix-4 multiplier in Verilog that cuts the number of partial products with Booth encoding and compresses them with TDM. Covers the Booth encoder and selector, partial product generation, the carry save adder, the Kogge-Stone final adder, and the accuracy verification waveforms.
Hardware ProjectCortex-M0 SoC Design: A Multifunction Robot Control System on AHB-Lite
Designed an SoC on a Basys3 board that combines a Cortex-M0 with AHB-Lite peripherals. Covers the HW and SW of a multifunction system that controls a small robot over UART and runs an up counter, a stopwatch, a random number generator/multiplier, and an adder/subtractor, along with the results.
Embedded NoteInside the ARM Processor: The 3-Stage Pipeline and Instruction Execution
Notes on the organization and implementation of ARM processors. Covers the main components such as the register file, barrel shifter, and ALU, the 3-stage pipeline, the memory bottleneck, the evolution to the 5-stage ARM9, data forwarding, and multiple load/store.
Embedded NoteRaspberry Pi Hardware: The Cache Hierarchy and ARM vs x86
Notes on Raspberry Pi hardware. Covers the BCM2711 SoC specs, L1 and L2 cache organization and associativity, ARM vs x86, Windows vs Linux, and Linux basics such as shell commands, file commands, pipes, and redirection.
Embedded NoteIntro to Raspberry Pi Hardware Hacking: GPIO, UART, I2C, and SPI
Introductory notes on hardware hacking: driving external devices directly from a Raspberry Pi. Covers how the GPIO, UART, I2C, and SPI buses work and where they fall short, controlling an LED circuit with wiringPi, and hands-on manipulation of the BCM2835 peripheral registers.
Embedded NoteInside the ARM Cortex-M3: Harvard Architecture, Registers, and xPSR
Notes on the structure of the ARMv7-M-based Cortex-M3. Covers its specifications, modified Harvard memory architecture, 3-stage pipeline, general-purpose registers R0~R12, the APSR, IPSR, and EPSR flags in xPSR, and the PRIMASK, FAULTMASK, and BASEPRI special registers.
Embedded NoteARM Assembly Basics: Instruction Format and Arithmetic/Logic Operations
Notes on the basics of ARM assembly programming. Covers instruction format and suffixes, arithmetic, logical, shift, and comparison operations, immediate value rules, shifted register operands, setting condition codes, addressing modes, and branches and subroutines, with examples.
Embedded NoteARM Architecture and Registers: Banked Registers by Processor Mode
Notes on the programmer's model of the ARM architecture. Covers the version lineage, visible registers, banked registers by processor mode, the PC and CPSR, supervisor mode, the load-store architecture, and data processing and control flow instructions.
Hardware ProjectDifferential Amplifier Design: 60 dB from a Mirror-Biased Two-Stage Amp
Designed a differential-input, single-ended-output amplifier with over 60 dB of gain in SIMetrix. The first stage is a differential amplifier biased with a current mirror and the second stage is a source-coupled amplifier, and I checked the output waveform for a 1 mV input at 5 V and 100 uA.
Hardware ProjectDesigning a Verilog Slot Machine: LFSR Random Numbers and a Timer Seed (Basys3)
I designed a slot machine for the Basys3 board in Verilog. A timer seeds an LFSR to produce three BCD random numbers, and the output is 2x, 5x, or 10x the input depending on how many digits match. Covers the block diagram, sub-block definitions, simulation waveforms, and discussion.
Hardware ProjectWallace Tree Multiplier in Verilog: 8-Bit Parallel Multiply with Adders
I designed an 8-bit parallel multiplier in Verilog using the Wallace tree structure, which reduces partial sums stage by stage with half adders and full adders. Covers the computation that produces the 16-bit product, the design flow, the testbench, and the full code.
Hardware ProjectA 5-Stage Pipelined RISC-V Processor in Verilog: Hazards and Forwarding
I designed a 5-stage pipelined RISC-V processor in Verilog that supports the full RV32I instruction set. This post covers resolving data and control hazards with a hazard detection unit and a forwarding unit, and verifying the design with iverilog and GTKWave waveforms.
Hardware ProjectAn 8-Bit Breadboard Computer Built from 74LS Chips: How a CPU Works
Following Ben Eater's design, I built an 8-bit computer on breadboards using only 74LS-series TTL chips. A record of learning the CPU's instruction execution cycle by wiring the clock, registers, ALU, RAM, program counter, and control unit by hand.
Web & App ProjectAndroid Restaurant Picker with Kakao Map and Naver Search APIs (Kotlin)
Mechu, an Android app built to answer "what should I eat today?" It finds restaurants near you with the Naver Local Search API, picks one at random with a single button, and shows it on Kakao Map. Covers location permissions, animation, category filters, and the release process.
Web & App ProjectBuilding a GitHub Pages + Jekyll Blog: From Repository to Auto-Deploy
A record of building my first blog with GitHub Pages + Jekyll. This post walks through setting up a GitHub Blog, a rite of passage for many developers. Why a GitHub Blog: to run a blog as a developer portfolio, the following conditions matter: - Tracking post history with version control...
Other ProjectDC Motor Position Controller: Meeting Settling Time with PID and Root Locus
I designed a position controller for a DC servo motor in MATLAB. Under the requirements of a damping ratio of 0.4–0.7, a settling time under 1/30 s, and a phase margin of at least 40 degrees, I found the PID gains with the root locus, checked that the requirements were met and searched for the optimum, and wrote up my reflections.
Other ProjectPower Generation and Transmission Planning: Objectives and Constraints
A generation and transmission planning project from a power systems engineering course. It models new power plants and transmission expansion to meet long-term demand growth as a cost-minimization problem, and covers the constraints, power flow calculation, MILP optimization, and scenario analysis.
Hardware ProjectZynq-7000 FPGA AI Accelerator: CNN/FC Cores and AXI CDMA Data Movement
I built an AI accelerator on a Zynq-7000 FPGA by designing CNN and fully connected compute cores and an AXI CDMA data mover. This post covers the Vivado and Vitis work: the design flow, the memory map, verifying the cores and movers, and building a 5-stage AI model.
Hardware ProjectBuilding a Raspberry Pi IoT Vending Machine: Firebase Stock and Theft Alerts
An IoT vending machine project built with a Raspberry Pi. It manages stock and revenue remotely through a Firebase database and, when it detects theft, sounds a siren and alerts the operator. Covers the parts list, the hardware layout on each side, and the Python control code.
Hardware ProjectKogge-Stone Adder in Verilog: Fewer Logic Levels with Higher-Valency Cells
I designed a Kogge-Stone adder, the tree adder with the fewest logic levels, in Verilog using higher-valency cells. Covers the bitwise PG, group PG, and SUM logic code, testbench waveform verification, and the performance optimizations and analysis.
Hardware Note26
View All →SoC NoteSoC NoteAMBA 3 AHB-Lite Bus Architecture: Signals and Transaction Behavior
Notes on AMBA 3 AHB-Lite, the standard system bus for Cortex-M0 and M3. Covers the single-master structure, master and slave signals, pipelined transactions and wait states, burst transfers and HTRANS, address decoding, and the AHB-APB bridge.
SoC NoteARM Cortex-M0 Architecture: Register Set, Operating Modes, Memory Map
Notes on the Cortex-M0, an ARMv6-M core for ultra-low-power MCUs. Covers its features and structure, register set, operating modes, memory map, exceptions and interrupts, the Thumb instruction set, the 3-stage pipeline, SysTick, and a comparison with the Cortex-M3 and M4.
SoC NoteClassifying the ARM Thumb Instruction Set: Data Processing Instructions
Notes classifying the Cortex-M0 Thumb instruction set by type. Covers the syntax and encoding of register, immediate, logical, shift, and multiply data processing instructions; basic, offset, multiple, and PC-relative loads and stores; and branch instructions.
SoC NoteComparing Chip Design Methodologies: Full-Custom, Standard-Cell, PLD
Notes on the semiconductor circuit design process and SoC design methodologies. Covers the steps from specification through layout, verification, and fabrication, a comparison of full-custom, standard-cell, and PLD approaches, and integrating internal vs. external IP and hard vs. soft IP.
Embedded NoteEmbedded NoteARM Architecture and Registers: Banked Registers by Processor Mode
Notes on the programmer's model of the ARM architecture. Covers the version lineage, visible registers, banked registers by processor mode, the PC and CPSR, supervisor mode, the load-store architecture, and data processing and control flow instructions.
Embedded NoteARM Assembly Basics: Instruction Format and Arithmetic/Logic Operations
Notes on the basics of ARM assembly programming. Covers instruction format and suffixes, arithmetic, logical, shift, and comparison operations, immediate value rules, shifted register operands, setting condition codes, addressing modes, and branches and subroutines, with examples.
Embedded NoteInside the ARM Cortex-M3: Harvard Architecture, Registers, and xPSR
Notes on the structure of the ARMv7-M-based Cortex-M3. Covers its specifications, modified Harvard memory architecture, 3-stage pipeline, general-purpose registers R0~R12, the APSR, IPSR, and EPSR flags in xPSR, and the PRIMASK, FAULTMASK, and BASEPRI special registers.
Embedded NoteInside the ARM Processor: The 3-Stage Pipeline and Instruction Execution
Notes on the organization and implementation of ARM processors. Covers the main components such as the register file, barrel shifter, and ALU, the 3-stage pipeline, the memory bottleneck, the evolution to the 5-stage ARM9, data forwarding, and multiple load/store.
Microprocessor NoteMicroprocessor NoteAMBA APB Protocol: Signals and Read/Write Transfer Timing
Notes on the AMBA 3 APB protocol. Covers the characteristics and signals of this bus for low-speed peripherals, read and write transfer timing with and without wait states, the APB slave state machine, the AHB-APB bridge, and a comparison of APB and AHB.
Microprocessor NoteCrossbar Bus Architecture: From Shared Bus to Full Matrix
Notes on the crossbar bus that connects multiple masters and slaves. Covers the evolution from shared bus to hierarchical bus to full matrix, the PL301 structure and arbitration schemes, pipelined and burst transfers, QoS, scaling to NoC, and clock domain crossing.
Microprocessor NoteDatapath Functional Units: Barrel Shifters, Comparators, Multipliers
Notes on the functional units of a processor datapath. Covers the structure and area/delay characteristics of barrel shifters, equality and magnitude comparators, array multipliers and Booth encoding, Wallace and Dadda trees, and restoring and non-restoring dividers.
Microprocessor NoteDigital Adder Design: Half/Full Adders and Ripple Carry Adder Delay
Notes on digital adder architectures. Covers half and full adders with propagate and generate, transistor-level design, and ripple carry adder delay, through carry lookahead, carry skip and carry select, and Brent-Kung and Kogge-Stone adders.
Computer Architecture NoteComputer Architecture NoteComputer Architecture Basics: ISA, Abstraction Layers, and Performance
Notes on the introduction to a computer architecture course. Covers abstract data types (ADTs) with a stack example, the instruction set architecture (ISA), Hennessy and Patterson's engineering methodology and its two golden rules, and performance evaluation methods and design techniques.
Computer Architecture NoteHow Virtual Memory Works: Paging and Virtual-to-Physical Translation
Notes on how virtual memory works. Covers paging, which splits the virtual address space into pages, translation from virtual to physical addresses, page table organization and the PTBR, the TLB, and the pros and cons of demand paging.
Computer Architecture NoteMemory Hierarchy and Caches: The Memory Wall and Four Cache Design Questions
Notes on the memory hierarchy and caches. Covers the memory wall and temporal and spatial locality, hierarchy terminology, the four questions of cache design (placement, identification, replacement, writes), a direct-mapped cache example, and how block size relates to miss rate.
Computer Architecture NoteMultiprocessors and Shared-Memory Sync: Critical Sections, Producer-Consumer
Notes on multiprocessor architecture. Covers UMA and NUMA shared memory, a sum reduction example, the producer-consumer and critical-section problems, Test-and-Set mutual exclusion and optimized synchronization, message passing and clusters, and interconnect structures.
Project23
View All →Hardware ProjectHardware ProjectA 5-Stage Pipelined RISC-V Processor in Verilog: Hazards and Forwarding
I designed a 5-stage pipelined RISC-V processor in Verilog that supports the full RV32I instruction set. This post covers resolving data and control hazards with a hazard detection unit and a forwarding unit, and verifying the design with iverilog and GTKWave waveforms.
Hardware ProjectAn 8-Bit Breadboard Computer Built from 74LS Chips: How a CPU Works
Following Ben Eater's design, I built an 8-bit computer on breadboards using only 74LS-series TTL chips. A record of learning the CPU's instruction execution cycle by wiring the clock, registers, ALU, RAM, program counter, and control unit by hand.
Hardware ProjectBuilding a Raspberry Pi IoT Vending Machine: Firebase Stock and Theft Alerts
An IoT vending machine project built with a Raspberry Pi. It manages stock and revenue remotely through a Firebase database and, when it detects theft, sounds a siren and alerts the operator. Covers the parts list, the hardware layout on each side, and the Python control code.
Hardware ProjectBuilding an Arduino Auto Fire Extinguisher: Flame, Smoke, Heat Sensing + IoT
KURUNG, an Arduino auto fire extinguisher entered in Sungkyunkwan University's 2021 Creative Capstone Design Competition. We built a low-cost IoT device that judges flame, smoke, and temperature sensors together to detect kitchen fires early, sprays extinguishing agent, and alerts a smartphone.
AI ProjectAI ProjectFederated Learning in Distributed Settings: Comparing FedProx and SCAFFOLD
I compared the performance of the FedProx and SCAFFOLD federated learning algorithms on non-IID data. Experiments used the AG News text classification dataset and a GRU model, and I analyzed each algorithm's convergence behavior.
AI ProjectImplementing Deep RL Algorithms: Comparing DQN, Double DQN, and PER
Compares three reinforcement learning algorithms, DQN, Double DQN, and PER, in the CartPole, Acrobot, and MountainCar environments, and analyzes the characteristics and limits of each.
AI ProjectNode Classification on a Knowledge Graph: Analyzing NELL with a GCN
I performed node classification on the NELL knowledge graph dataset with a GCN (Graph Convolutional Network). I implemented the model in PyTorch Geometric and reached 97.86% test accuracy on 65,755 nodes and 186 classes.
Web & App ProjectWeb & App ProjectAndroid Restaurant Picker with Kakao Map and Naver Search APIs (Kotlin)
Mechu, an Android app built to answer "what should I eat today?" It finds restaurants near you with the Naver Local Search API, picks one at random with a single button, and shows it on Kakao Map. Covers location permissions, animation, category filters, and the release process.
Web & App ProjectBuilding a GitHub Pages + Jekyll Blog: From Repository to Auto-Deploy
A record of building my first blog with GitHub Pages + Jekyll. This post walks through setting up a GitHub Blog, a rite of passage for many developers. Why a GitHub Blog: to run a blog as a developer portfolio, the following conditions matter: - Tracking post history with version control...
Web & App ProjectBuilding a Lab Website: An Academic Site on WordPress
I built the website of the Intelligent Systems Lab at Yonsei University on WordPress, implementing research area pages, member management, a publication archive, and news/gallery features.
Web & App ProjectBuilding a Personal Tech Blog: A Full-Stack Web Application on Django
I built a personal tech blog with Django and plain JavaScript/CSS. I implemented Markdown-based writing, hierarchical categories, AI features (Gemini), and SEO optimization myself.
Other ProjectOther ProjectBuilding a Guessing Game System Based on Human-Robot Interaction
I helped develop a guessing game system based on human-robot interaction that combines YOLO object detection with a VLM (vision-language model). We built a game in which the robot arm infers and points to an object from the user's clues.
Other ProjectDC Motor Position Controller: Meeting Settling Time with PID and Root Locus
I designed a position controller for a DC servo motor in MATLAB. Under the requirements of a damping ratio of 0.4–0.7, a settling time under 1/30 s, and a phase margin of at least 40 degrees, I found the PID gains with the root locus, checked that the requirements were met and searched for the optimum, and wrote up my reflections.
Other ProjectDesigning a Rectilinear Steiner Tree Algorithm for VLSI Routing
I implemented a Dijkstra-based Rectilinear Steiner Minimum Tree (RSMT) algorithm for routing optimization in VLSI design. It minimizes total wirelength by selecting Steiner candidate points from the Hanan grid and optimizing iteratively.
Other ProjectPower Generation and Transmission Planning: Objectives and Constraints
A generation and transmission planning project from a power systems engineering course. It models new power plants and transmission expansion to meet long-term demand growth as a cost-minimization problem, and covers the constraints, power flow calculation, MILP optimization, and scenario analysis.
Digital Design22
View All →RISC-VRISC-VAssembly and the ABI: Registers, Calling Convention, Stack Frames, ELF
Part 6 of the RISC-V series. I follow the psABI calling convention and stack frame through real C functions. The work() frame was 80 bytes, and arguments from the 9th onward went on the stack. I checked argument locations per ABI and relocations, and linker relaxation shrank .text from 800 bytes to 712 bytes.
RISC-VC Extension: Decompressor, 16-Bit Fetch, and Misaligned 32-Bit Instructions
Part 21 of the RISC-V series. I built the C extension's decompressor and fetch buffer in Python and checked all 49,152 16-bit values and a real rv32imc program against objdump. 36.7% of executed instructions spanned two words, and the fetch buffer cut word reads from 33,771 to 23,903.
RISC-VF and D Extensions: FP Registers, Rounding, fcsr Flags, NaN Boxing
Part 10 of the RISC-V series. I ran 229 instructions on QEMU covering the F and D extensions' rounding modes and exception flags, the canonical NaN, NaN boxing, and saturation rules for out-of-range integer conversion, and confirmed that all of them matched an exact-fraction reference model.
RISC-VFENCE.I and Self-Modifying Code: What the Instruction Side Must Honor
Part 22 of the RISC-V series. Covers FENCE.I and self-modifying code. Without fence.i, QEMU ran the new code when it was written elsewhere but the old code inside the block being executed. Running 16 combinations on an instruction-set model, I identified the minimal FENCE.I implementation for each core organization.