Skip to content
HomePortfolioPostCompositionPhotos
한국어
System Blog logoSunhong'sSystem Blog
HomePortfolioPost
Hobby
CompositionSongs I wrotePhotosPhotos I took
KOEN
Today
한국어로 보기
Contents
  • Project 23
    • Hardware Project 12
      • Building an Arduino Auto Fire Extinguisher: Flame, Smoke, Heat Sensing + IoT
      • Radix-8 Booth Multiplier: Encoding Table and TDM Trade-offs (Verilog)
      • Radix-4 Booth Multiplier: Partial Product Reduction with TDM (Verilog)
      • Cortex-M0 SoC Design: A Multifunction Robot Control System on AHB-Lite
      • Differential Amplifier Design: 60 dB from a Mirror-Biased Two-Stage Amp
      • Designing a Verilog Slot Machine: LFSR Random Numbers and a Timer Seed (Basys3)
      • Wallace Tree Multiplier in Verilog: 8-Bit Parallel Multiply with Adders
      • A 5-Stage Pipelined RISC-V Processor in Verilog: Hazards and Forwarding
      • An 8-Bit Breadboard Computer Built from 74LS Chips: How a CPU Works
      • Zynq-7000 FPGA AI Accelerator: CNN/FC Cores and AXI CDMA Data Movement
      • Building a Raspberry Pi IoT Vending Machine: Firebase Stock and Theft Alerts
      • Kogge-Stone Adder in Verilog: Fewer Logic Levels with Higher-Valency Cells
    • AI Project 3
      • Federated Learning in Distributed Settings: Comparing FedProx and SCAFFOLD
      • Node Classification on a Knowledge Graph: Analyzing NELL with a GCN
      • Implementing Deep RL Algorithms: Comparing DQN, Double DQN, and PER
    • Web & App Project 4
      • Building a Lab Website: An Academic Site on WordPress
      • Building a Personal Tech Blog: A Full-Stack Web Application on Django
      • Android Restaurant Picker with Kakao Map and Naver Search APIs (Kotlin)
      • Building a GitHub Pages + Jekyll Blog: From Repository to Auto-Deploy
    • Other Project 4
      • Building a Guessing Game System Based on Human-Robot Interaction
      • Designing a Rectilinear Steiner Tree Algorithm for VLSI Routing
      • DC Motor Position Controller: Meeting Settling Time with PID and Root Locus
      • Power Generation and Transmission Planning: Objectives and Constraints
  • AI Note 2
    • Neural Network Basics: From the Perceptron to Multilayer Networks
    • Backpropagation: Gradients via the Chain Rule and MNIST in NumPy
  • Hardware Note 26
    • SoC Note 8
      • ARM Cortex-M0 Architecture: Register Set, Operating Modes, Memory Map
      • SoC Design Frameworks and the Design Productivity Gap
      • SoC Programming in C: Controlling Memory-Mapped I/O Registers
      • Classifying the ARM Thumb Instruction Set: Data Processing Instructions
      • AMBA 3 AHB-Lite Bus Architecture: Signals and Transaction Behavior
      • Processor vs. Core: Instruction Stages and Layers of Abstraction
      • Comparing Chip Design Methodologies: Full-Custom, Standard-Cell, PLD
      • Cortex-M NVIC Interrupt Handling: Vector Table and Exception Priority
    • Embedded Note 7
      • Intro to ARM Embedded Systems: ARM vs. Thumb Instruction Sets
      • Inside the ARM Processor: The 3-Stage Pipeline and Instruction Execution
      • Raspberry Pi Hardware: The Cache Hierarchy and ARM vs x86
      • Intro to Raspberry Pi Hardware Hacking: GPIO, UART, I2C, and SPI
      • Inside the ARM Cortex-M3: Harvard Architecture, Registers, and xPSR
      • ARM Assembly Basics: Instruction Format and Arithmetic/Logic Operations
      • ARM Architecture and Registers: Banked Registers by Processor Mode
    • Microprocessor Note 5
      • Crossbar Bus Architecture: From Shared Bus to Full Matrix
      • AMBA APB Protocol: Signals and Read/Write Transfer Timing
      • Digital Adder Design: Half/Full Adders and Ripple Carry Adder Delay
      • How CMOS Transistors Work: From the PN Junction to nMOS/pMOS
      • Datapath Functional Units: Barrel Shifters, Comparators, Multipliers
    • Computer Architecture Note 6
      • Computer Architecture Basics: ISA, Abstraction Layers, and Performance
      • How Virtual Memory Works: Paging and Virtual-to-Physical Translation
      • Memory Hierarchy and Caches: The Memory Wall and Four Cache Design Questions
      • Pipelining and Hazards: Analyzing the 5-Stage MIPS Pipeline
      • Multiprocessors and Shared-Memory Sync: Critical Sections, Producer-Consumer
      • Storage and I/O System Architecture: I/O Buses and Reliability (MTTF)
  • Digital Design 22
    • RISC-V 22
      • RISC-V Overview: The Spec, ISA Names, and What Extensions Do to Code
      • RV32I 1: Registers, Six Instruction Formats, and Why Immediates Are Scrambled
      • RV32I 2: Integer Ops, Compares, Shifts, and Building Constants with lui/auipc
      • RV32I 3: Branches, Jumps, Loads/Stores and Alignment, FENCE, ECALL/EBREAK
      • RV64I: W Instructions, Sign-Extension Rules, and What Differs from 32-Bit
      • Assembly and the ABI: Registers, Calling Convention, Stack Frames, ELF
      • The M Extension: Multiply, Divide, and the Rules for Divide-by-Zero and Overflow
      • The A Extension: LR/SC, AMOs, and aq/rl
      • The Memory Model: RVWMO, What FENCE Means, and Ztso
      • F and D Extensions: FP Registers, Rounding, fcsr Flags, NaN Boxing
      • The C Extension: Compressed Formats and Their 32-bit Equivalents
      • Small Extensions: Zicsr, Zifencei, Zicntr·Zihpm, B (Zba·Zbb·Zbs), Zicond, Zicbom
      • V Extension 1: VLEN, SEW, LMUL, vsetvli, and Vector-Length-Agnostic Code
      • V Extension 2: Masks, Load/Store Types, Reductions, Permutes, Tail/Mask Agnostic
      • RISC-V Decoder Design: Decode Tables, Formats, and Illegal Instructions
      • The Immediate Generator and a RISC-V Single-Cycle Datapath
      • RISC-V 5-Stage Pipeline: Forwarding and Stall Conditions, Handling x0
      • RISC-V Branches and Jumps: Resolve Stage, JAL/JALR, Return-Address Stack Hints
      • Implementing the M Extension: Multiply/Divide Units and Divide-by-Zero
      • Implementing the A Extension: Reservations, Where AMOs Run, aq/rl, FENCE
      • C Extension: Decompressor, 16-Bit Fetch, and Misaligned 32-Bit Instructions
      • FENCE.I and Self-Modifying Code: What the Instruction Side Must Honor
Double-click to collapseCtrl[
Posts/AI Note

AI Note

2 posts·From CNNs to LLMs
AI Note · 2
NewestA-ZZ-APopular

: no matching posts.

Clear filters
AI Note
Nov 3, 2026

Neural Network Basics: From the Perceptron to Multilayer Networks

Part 1 of AI Note. Starting from a single neuron's weighted sum and activation, we follow why the perceptron cannot solve XOR and how stacking layers solves it, softmax and cross-entropy loss, and gradient descent under different learning rates, all with numeric examples worked out by hand.

AI Note
Nov 3, 2026

Backpropagation: Gradients via the Chain Rule and MNIST in NumPy

Part 2 of AI Note. We follow backpropagation through the chain rule and computational graphs, starting from numeric examples, derive the gradients of a two-layer network in matrix form, and implement it from scratch in NumPy to reach 97.7% on MNIST. We also measure why minibatches are fast.

Sunhong's System Blog

AI · Hardware · Development

Read the postsPortfolio

Blog

HomePostPortfolio

Project

Hardware ProjectAI ProjectWeb & App ProjectOther Project

AI Note

Hardware Note

SoC NoteEmbedded NoteMicroprocessor NoteComputer Architecture Note

Digital Design

RISC-V

Hobby

CompositionPhotos

Site

AboutContactPrivacyRSSGitHubLinkedIn
System Blog© 2026 SunhongAstro · TypeScript · Cloudflare
Enlarged image