AMBA 3 AHB-Lite Bus Architecture: Signals and Transaction Behavior

Chapter 7 AMBA 3 AHB-Lite Bus Architecture Overview

AHB-Lite is the single-master version of the ARM AMBA (Advanced Microcontroller Bus Architecture) 3.0 standard. It is the standard system bus for Cortex-M0/M3 MCUs.

AMBA 3 AHB-Lite Features

• Single-master bus: the original AHB was multi-master, but Lite has a single master (no arbiter)
• Pipelined transactions: the address phase and data phase overlap → ↑ throughput
• Supports burst transfers (INCR, WRAP)
• No split transactions (in the Lite version)

Signal Description

Master Output

• HCLK: bus clock
• HRESETn: active-low reset
• HADDR[31:0]: address
• HWRITE: 1=write, 0=read
• HSIZE[2:0]: transfer size (byte/halfword/word)
• HBURST[2:0]: burst type (SINGLE, INCR, WRAP4, INCR4, …)
• HPROT[3:0]: protection/cache attribute
• HTRANS[1:0]: transfer type (IDLE, BUSY, NONSEQ, SEQ)
• HWDATA[31:0]: write data
• HMASTLOCK: locked transaction

Slave Output

• HRDATA[31:0]: read data
• HREADY: slave ready (wait state)
• HRESP: response (OKAY, ERROR)

AHB-Lite Transaction

A basic transaction takes 2 cycles: an address phase and a data phase:

     T0        T1        T2
HCLK __/\__/\__/\__/\__
HADDR ___[Addr]________
HWRITE __[____1_____]____
HTRANS ___[NONSEQ]__[IDLE]_
HWDATA __________[Data]__
HREADY ___________/‾‾‾\_

• T1 (Address phase): the master drives the address and control
• T2 (Data phase): the slave drives or accepts the data and signals completion with HREADY

Wait State

If the slave is not ready, it holds HREADY=0 → the data phase is extended.

Burst Transfer

Transfers several consecutive words as one NONSEQ + several SEQ:

Burst Type (HBURST)

• SINGLE: single transfer
• INCR: unspecified length increment
• WRAP4: 4-beat wrapping (cache line)
• INCR4: 4-beat incrementing
• WRAP8, INCR8, WRAP16, INCR16: fixed lengths

HTRANS

• IDLE: no transfer
• BUSY: pause in the middle of a burst
• NONSEQ: start of a burst or a single transfer
• SEQ: subsequent transfer within a burst (address increments)

AHB-Lite System Organization

                [AHB Master]
                  │ AHB
                  ▼
         ┌─── [Decoder] ─── HSELx
         │                     │
        [MUX]               [AHB Slave 1]
         │                  [AHB Slave 2]
         │                  [AHB Slave 3]
         ▼
  (HRDATA, HREADY, HRESP)

• Decoder: decodes HADDR and asserts the HSEL of the matching slave
• MUX: routes the selected slave's HRDATA, HREADY, and HRESP to the master

HSELx & Address Decode

Each slave is assigned its own address range. The decoder selects HSEL from the upper bits of HADDR:

if (HADDR[31:20] == 0x400)
    HSEL_UART = 1;
else if (HADDR[31:20] == 0x401)
    HSEL_GPIO = 1;

AHB to APB Bridge

Connects AHB-Lite to the low-speed APB. The bridge acts as an AHB master and communicates with the APB slaves. The typical structure of a Cortex-M0 SoC:

[Cortex-M0 Core]
      │ AHB-Lite
      ▼
 [AHB Interconnect]
  │ │ │ 
  │ │ └── SRAM
  │ └───── Flash
  └─────── AHB→APB Bridge
             │ APB
             ├── UART
             ├── Timer
             ├── GPIO
             └── SPI/I2C

HPROT (Protection Signals)

Indicates cacheability/bufferability, user/privileged, and data/opcode:

• HPROT[0]: opcode fetch (0) / data access (1)
• HPROT[1]: user (0) / privileged (1)
• HPROT[2]: non-bufferable (0) / bufferable (1)
• HPROT[3]: non-cacheable (0) / cacheable (1)

HRESP

• OKAY (0): normal completion
• ERROR (1): slave error — the master receives the error response as a 2-cycle sequence

Summary

AHB-Lite is the default bus of Cortex-M0/M3 SoCs. It is simple yet provides enough bandwidth, which makes it a good fit for low-power embedded systems.