Project
: no matching posts.
Clear filters
AI ProjectFederated Learning in Distributed Settings: Comparing FedProx and SCAFFOLD
I compared the performance of the FedProx and SCAFFOLD federated learning algorithms on non-IID data. Experiments used the AG News text classification dataset and a GRU model, and I analyzed each algorithm's convergence behavior.
AI ProjectNode Classification on a Knowledge Graph: Analyzing NELL with a GCN
I performed node classification on the NELL knowledge graph dataset with a GCN (Graph Convolutional Network). I implemented the model in PyTorch Geometric and reached 97.86% test accuracy on 65,755 nodes and 186 classes.
Other ProjectBuilding a Guessing Game System Based on Human-Robot Interaction
I helped develop a guessing game system based on human-robot interaction that combines YOLO object detection with a VLM (vision-language model). We built a game in which the robot arm infers and points to an object from the user's clues.
Other ProjectDesigning a Rectilinear Steiner Tree Algorithm for VLSI Routing
I implemented a Dijkstra-based Rectilinear Steiner Minimum Tree (RSMT) algorithm for routing optimization in VLSI design. It minimizes total wirelength by selecting Steiner candidate points from the Hanan grid and optimizing iteratively.
Web & App ProjectBuilding a Lab Website: An Academic Site on WordPress
I built the website of the Intelligent Systems Lab at Yonsei University on WordPress, implementing research area pages, member management, a publication archive, and news/gallery features.
Web & App ProjectBuilding a Personal Tech Blog: A Full-Stack Web Application on Django
I built a personal tech blog with Django and plain JavaScript/CSS. I implemented Markdown-based writing, hierarchical categories, AI features (Gemini), and SEO optimization myself.
AI ProjectImplementing Deep RL Algorithms: Comparing DQN, Double DQN, and PER
Compares three reinforcement learning algorithms, DQN, Double DQN, and PER, in the CartPole, Acrobot, and MountainCar environments, and analyzes the characteristics and limits of each.
Hardware ProjectBuilding an Arduino Auto Fire Extinguisher: Flame, Smoke, Heat Sensing + IoT
KURUNG, an Arduino auto fire extinguisher entered in Sungkyunkwan University's 2021 Creative Capstone Design Competition. We built a low-cost IoT device that judges flame, smoke, and temperature sensors together to detect kitchen fires early, sprays extinguishing agent, and alerts a smartphone.
Hardware ProjectRadix-8 Booth Multiplier: Encoding Table and TDM Trade-offs (Verilog)
I designed a multiplier in Verilog that combines Radix-8 Booth encoding with TDM. This post covers how the Booth algorithm works, the number of partial products and hardware trade-offs at each radix, the Radix-8 encoding table, implementation and verification, and lessons learned.
Hardware ProjectRadix-4 Booth Multiplier: Partial Product Reduction with TDM (Verilog)
I designed a radix-4 multiplier in Verilog that cuts the number of partial products with Booth encoding and compresses them with TDM. Covers the Booth encoder and selector, partial product generation, the carry save adder, the Kogge-Stone final adder, and the accuracy verification waveforms.
Hardware ProjectCortex-M0 SoC Design: A Multifunction Robot Control System on AHB-Lite
Designed an SoC on a Basys3 board that combines a Cortex-M0 with AHB-Lite peripherals. Covers the HW and SW of a multifunction system that controls a small robot over UART and runs an up counter, a stopwatch, a random number generator/multiplier, and an adder/subtractor, along with the results.
Hardware ProjectDifferential Amplifier Design: 60 dB from a Mirror-Biased Two-Stage Amp
Designed a differential-input, single-ended-output amplifier with over 60 dB of gain in SIMetrix. The first stage is a differential amplifier biased with a current mirror and the second stage is a source-coupled amplifier, and I checked the output waveform for a 1 mV input at 5 V and 100 uA.
Hardware ProjectDesigning a Verilog Slot Machine: LFSR Random Numbers and a Timer Seed (Basys3)
I designed a slot machine for the Basys3 board in Verilog. A timer seeds an LFSR to produce three BCD random numbers, and the output is 2x, 5x, or 10x the input depending on how many digits match. Covers the block diagram, sub-block definitions, simulation waveforms, and discussion.
Hardware ProjectWallace Tree Multiplier in Verilog: 8-Bit Parallel Multiply with Adders
I designed an 8-bit parallel multiplier in Verilog using the Wallace tree structure, which reduces partial sums stage by stage with half adders and full adders. Covers the computation that produces the 16-bit product, the design flow, the testbench, and the full code.
Hardware ProjectA 5-Stage Pipelined RISC-V Processor in Verilog: Hazards and Forwarding
I designed a 5-stage pipelined RISC-V processor in Verilog that supports the full RV32I instruction set. This post covers resolving data and control hazards with a hazard detection unit and a forwarding unit, and verifying the design with iverilog and GTKWave waveforms.
Hardware ProjectAn 8-Bit Breadboard Computer Built from 74LS Chips: How a CPU Works
Following Ben Eater's design, I built an 8-bit computer on breadboards using only 74LS-series TTL chips. A record of learning the CPU's instruction execution cycle by wiring the clock, registers, ALU, RAM, program counter, and control unit by hand.
Web & App ProjectAndroid Restaurant Picker with Kakao Map and Naver Search APIs (Kotlin)
Mechu, an Android app built to answer "what should I eat today?" It finds restaurants near you with the Naver Local Search API, picks one at random with a single button, and shows it on Kakao Map. Covers location permissions, animation, category filters, and the release process.
Web & App ProjectBuilding a GitHub Pages + Jekyll Blog: From Repository to Auto-Deploy
A record of building my first blog with GitHub Pages + Jekyll. This post walks through setting up a GitHub Blog, a rite of passage for many developers. Why a GitHub Blog: to run a blog as a developer portfolio, the following conditions matter: - Tracking post history with version control...
Other ProjectDC Motor Position Controller: Meeting Settling Time with PID and Root Locus
I designed a position controller for a DC servo motor in MATLAB. Under the requirements of a damping ratio of 0.4–0.7, a settling time under 1/30 s, and a phase margin of at least 40 degrees, I found the PID gains with the root locus, checked that the requirements were met and searched for the optimum, and wrote up my reflections.
Other ProjectPower Generation and Transmission Planning: Objectives and Constraints
A generation and transmission planning project from a power systems engineering course. It models new power plants and transmission expansion to meet long-term demand growth as a cost-minimization problem, and covers the constraints, power flow calculation, MILP optimization, and scenario analysis.
Hardware ProjectZynq-7000 FPGA AI Accelerator: CNN/FC Cores and AXI CDMA Data Movement
I built an AI accelerator on a Zynq-7000 FPGA by designing CNN and fully connected compute cores and an AXI CDMA data mover. This post covers the Vivado and Vitis work: the design flow, the memory map, verifying the cores and movers, and building a 5-stage AI model.
Hardware ProjectBuilding a Raspberry Pi IoT Vending Machine: Firebase Stock and Theft Alerts
An IoT vending machine project built with a Raspberry Pi. It manages stock and revenue remotely through a Firebase database and, when it detects theft, sounds a siren and alerts the operator. Covers the parts list, the hardware layout on each side, and the Python control code.
Hardware ProjectKogge-Stone Adder in Verilog: Fewer Logic Levels with Higher-Valency Cells
I designed a Kogge-Stone adder, the tree adder with the fewest logic levels, in Verilog using higher-valency cells. Covers the bitwise PG, group PG, and SUM logic code, testbench waveform verification, and the performance optimizations and analysis.