Experience
System-on-Chip Design Engineer
FADU · Datacenter SSD controller SoC, SoC Platform
Next-gen SoC: 2-wire management interface integration and design
- Reviewing the IP configuration of I2C, SMBus and I3C for instance count and security requirements, along with the AMBA interconnect and address map
- Defining open-drain/push-pull muxing rules for multiple I3C cores and SMBus sharing one pad, including the pad and external board components
- Moving FW-polled mode switching into HW with bus-state detection logic, an FSM and an APB register map, with CDC and handshakes across clock domains (implementation and verification in progress)
- Verifying with cocotb using AXI/APB drivers and FW-driven tests; lint and CDC checks with SpyGlass
Production SoC: error analysis and error injector design
- Found an error through exception-scenario verification of HDR transfers and located the fix points in the gate-level netlist
- Designed an HW error injector that injects bit-level errors at a register-selected transfer position (APB register map defined with FW); verified hang-free recovery across 8 error types (26 cases)
Open-source I3C IP verification environment
- Built a container-based environment to verify an open-source I3C IP in-house and shared it with the team; passed 24 top-level tests and found one unreported upstream defect
Graduate Researcher
Intelligent Systems Lab (Prof. Kyuho Lee, now at Yonsei University), M.S. program at UNIST isl-yonsei.ac ↗
Design and verification of a compute-in-memory processor for LLM acceleration
- Analyzed LLM vectors and applied quantization in PyTorch to develop an optimal compute algorithm through SW–HW co-design, cutting external memory access by 85.86%
- Designed the eDRAM cell array and peripheral circuits such as wordline/bitline drivers in Cadence Virtuoso with layout verification, and implemented the design in RTL with Synopsys tools
- Cut system latency by 77.27% through pipelining and parallelization
- Developed a compute-in-memory processor with 2-row parallel computation, improving energy efficiency by 1.58×
28nm hybrid CIM-NPU MPW tape-out (4-person team; RTL for the NPU core and CIM memory controller)
- Traced 112 of 127 setup violations to a 6-stage MUX chain in the transpose network and restructured the pipeline to reach zero (WNS +0.08 ns)
- Cut routing congestion from 23% to 8% in ICC2 by flattening hierarchy, fixed antenna DRC and signed off
- Built a cycle-by-cycle, bit-exact comparison between a C++ reference model and RTL, with Python regression automation
- Set up the test board/FPGA/host measurement flow; shmoo over 0.7–1.0 V and 100–500 MHz confirmed 500 MHz operation and 70.2 TOPS/W
Education
M.S. in Electrical Engineering
UNIST · Ulsan National Institute of Science and Technology, Department of Electrical Engineering
B.S. in Electrical Engineering
Dankook University · School of Electronic and Electrical Engineering
Publications
Journal · IEEE TVLSI 20261st author
CINELL: An Energy-Efficient Compute-In/Near-Memory eDRAM Processor for Sparse Transformer-Based Large Language Models
Sunhong An, Hoichang Jeong, Seungbin Kim, and Kyuho Lee
Conference · IEEE ISCAS 2025 · Oral1st author
A 46 TOPS/W In-/Near-Memory Computing Processor for Large Language Model with Extended Sparse Attention
Sunhong An, Hoichang Jeong, Seungbin Kim, Keonhee Park, Dongwook Kim, and Kyuho Lee
Conference · IEEE ISCAS 2025
A 0.74 µJ/decision and 22.59 TOPS/W Keyword Spotting CIM Processor with Short-Current-Free Multi-level ReRAM and Adaptive-Decision-Level Nonlinear ADC
Dongwook Kim, Hoichang Jeong, Seungbin Kim, Keonhee Park, Sunhong An, and Kyuho Lee
Domestic conference · The Institute of Semiconductor Engineers 20251st author
Computing-in-Memory Processor for Large Language Models with Sparse Attention (in Korean)
Sunhong An, Kyuho Lee
Awards & Scholarships
IEEE TVLSI Highlight Paper
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
First-author paper 'CINELL' selected as a Highlight Paper of IEEE TVLSI Vol. 34, No. 1, chosen by the editorial board for its technical contribution and completeness.
Honors Award
Dankook University
College honors award for academic excellence: major GPA 4.21, within the top 10% of the department.
Bronze Prize · Creative Capstone Design Competition
Sungkyunkwan University, Center for Innovation in Engineering Education
Automatic fire-detection and extinguishing device (4-person team, circuits): designed the buck converter power stage and the H-bridge motor driver.
Excellence Award · Top 3
Codeit University Coding Camp
Ran a large-scale data preprocessing and visualization project with Python, Pandas and Matplotlib; selected as one of the top 3 participants for code reliability.
Scholarships
Danwoo Scholarship · 2023 (twice) · Special Academic Scholarship · 2022 (twice)
Certifications
Computer Proficiency Certificate, Level 1
Korea Chamber of Commerce and Industry
ADsP · Advanced Data Analytics Semi-Professional
Korea Data Agency
Skills
- Synopsys
- VCS + VerdiSpyGlassDesign CompilerICC2StarRCPrimeTime
- Cadence
- Virtuoso ADESpectreInnovusXcelium
- Xilinx
- VivadoVitisILA
- Programming
- PythonPyTorchC/C++VerilogSystemVerilogTclcocotbJava/KotlinJavaScriptMatlab
- PCB
- KiCADEasyEDA
- Others
- Memory CompilerLinuxGitMakefile
Courses
- IDEC SoC Design Curriculum · 12 courses completed2022.06 – 2026.01
- Deep Learning Foundation and Design
- Verilog HDL Basic and Deep Learning Neural Network Design
- Embedded System Design Based on FPGA
- Embedded Memory (SRAM) Foundation
- Artificial Intelligence Acceleration Processor
- CUDA-based GPU programming foundation
- Layout Design for Full Custom IC Design
- Analog and digital circuit design practicum · Comento2023.07 – 2023.09
- Analog amplifier design and gain–linearity–power trade-off analysis
- Arithmetic blocks and FSMs in Verilog
- Design verification through analog and digital circuit simulation
- Online
- Object-Oriented Programming and Design (Java) · Udemy
- The Complete Practical Guide to Git & GitHub · Udemy
- High-Level Synthesis for FPGA · Udemy
- Hands-on HW Accelerator Design with FPGA · Inflearn
- The AI HW Design Bible: Mastering CNN Computation · Inflearn
- Hands-on Verilog HDL Season 2 (Mastering AMBA AXI4) · Inflearn
Projects
Hardware Project
Hardware ProjectBuilding an Arduino Auto Fire Extinguisher: Flame, Smoke, Heat Sensing + IoT
KURUNG, an Arduino auto fire extinguisher entered in Sungkyunkwan University's 2021 Creative Capstone Design Competition. We built a low-cost IoT device that judges flame, smoke, and temperature sensors together to detect kitchen fires early, sprays extinguishing agent, and alerts a smartphone.
Hardware ProjectRadix-8 Booth Multiplier: Encoding Table and TDM Trade-offs (Verilog)
I designed a multiplier in Verilog that combines Radix-8 Booth encoding with TDM. This post covers how the Booth algorithm works, the number of partial products and hardware trade-offs at each radix, the Radix-8 encoding table, implementation and verification, and lessons learned.
Hardware ProjectRadix-4 Booth Multiplier: Partial Product Reduction with TDM (Verilog)
I designed a radix-4 multiplier in Verilog that cuts the number of partial products with Booth encoding and compresses them with TDM. Covers the Booth encoder and selector, partial product generation, the carry save adder, the Kogge-Stone final adder, and the accuracy verification waveforms.
Hardware ProjectCortex-M0 SoC Design: A Multifunction Robot Control System on AHB-Lite
Designed an SoC on a Basys3 board that combines a Cortex-M0 with AHB-Lite peripherals. Covers the HW and SW of a multifunction system that controls a small robot over UART and runs an up counter, a stopwatch, a random number generator/multiplier, and an adder/subtractor, along with the results.
Hardware ProjectDifferential Amplifier Design: 60 dB from a Mirror-Biased Two-Stage Amp
Designed a differential-input, single-ended-output amplifier with over 60 dB of gain in SIMetrix. The first stage is a differential amplifier biased with a current mirror and the second stage is a source-coupled amplifier, and I checked the output waveform for a 1 mV input at 5 V and 100 uA.
Hardware ProjectDesigning a Verilog Slot Machine: LFSR Random Numbers and a Timer Seed (Basys3)
I designed a slot machine for the Basys3 board in Verilog. A timer seeds an LFSR to produce three BCD random numbers, and the output is 2x, 5x, or 10x the input depending on how many digits match. Covers the block diagram, sub-block definitions, simulation waveforms, and discussion.
Hardware ProjectWallace Tree Multiplier in Verilog: 8-Bit Parallel Multiply with Adders
I designed an 8-bit parallel multiplier in Verilog using the Wallace tree structure, which reduces partial sums stage by stage with half adders and full adders. Covers the computation that produces the 16-bit product, the design flow, the testbench, and the full code.
Hardware ProjectA 5-Stage Pipelined RISC-V Processor in Verilog: Hazards and Forwarding
I designed a 5-stage pipelined RISC-V processor in Verilog that supports the full RV32I instruction set. This post covers resolving data and control hazards with a hazard detection unit and a forwarding unit, and verifying the design with iverilog and GTKWave waveforms.
Hardware ProjectAn 8-Bit Breadboard Computer Built from 74LS Chips: How a CPU Works
Following Ben Eater's design, I built an 8-bit computer on breadboards using only 74LS-series TTL chips. A record of learning the CPU's instruction execution cycle by wiring the clock, registers, ALU, RAM, program counter, and control unit by hand.
Hardware ProjectZynq-7000 FPGA AI Accelerator: CNN/FC Cores and AXI CDMA Data Movement
I built an AI accelerator on a Zynq-7000 FPGA by designing CNN and fully connected compute cores and an AXI CDMA data mover. This post covers the Vivado and Vitis work: the design flow, the memory map, verifying the cores and movers, and building a 5-stage AI model.
Hardware ProjectBuilding a Raspberry Pi IoT Vending Machine: Firebase Stock and Theft Alerts
An IoT vending machine project built with a Raspberry Pi. It manages stock and revenue remotely through a Firebase database and, when it detects theft, sounds a siren and alerts the operator. Covers the parts list, the hardware layout on each side, and the Python control code.
Hardware ProjectKogge-Stone Adder in Verilog: Fewer Logic Levels with Higher-Valency Cells
I designed a Kogge-Stone adder, the tree adder with the fewest logic levels, in Verilog using higher-valency cells. Covers the bitwise PG, group PG, and SUM logic code, testbench waveform verification, and the performance optimizations and analysis.
AI Project
AI ProjectFederated Learning in Distributed Settings: Comparing FedProx and SCAFFOLD
I compared the performance of the FedProx and SCAFFOLD federated learning algorithms on non-IID data. Experiments used the AG News text classification dataset and a GRU model, and I analyzed each algorithm's convergence behavior.
AI ProjectNode Classification on a Knowledge Graph: Analyzing NELL with a GCN
I performed node classification on the NELL knowledge graph dataset with a GCN (Graph Convolutional Network). I implemented the model in PyTorch Geometric and reached 97.86% test accuracy on 65,755 nodes and 186 classes.
AI ProjectImplementing Deep RL Algorithms: Comparing DQN, Double DQN, and PER
Compares three reinforcement learning algorithms, DQN, Double DQN, and PER, in the CartPole, Acrobot, and MountainCar environments, and analyzes the characteristics and limits of each.
Web & App Project
Web & App ProjectBuilding a Lab Website: An Academic Site on WordPress
I built the website of the Intelligent Systems Lab at Yonsei University on WordPress, implementing research area pages, member management, a publication archive, and news/gallery features.
Web & App ProjectBuilding a Personal Tech Blog: A Full-Stack Web Application on Django
I built a personal tech blog with Django and plain JavaScript/CSS. I implemented Markdown-based writing, hierarchical categories, AI features (Gemini), and SEO optimization myself.
Web & App ProjectAndroid Restaurant Picker with Kakao Map and Naver Search APIs (Kotlin)
Mechu, an Android app built to answer "what should I eat today?" It finds restaurants near you with the Naver Local Search API, picks one at random with a single button, and shows it on Kakao Map. Covers location permissions, animation, category filters, and the release process.
Web & App ProjectBuilding a GitHub Pages + Jekyll Blog: From Repository to Auto-Deploy
A record of building my first blog with GitHub Pages + Jekyll. This post walks through setting up a GitHub Blog, a rite of passage for many developers. Why a GitHub Blog: to run a blog as a developer portfolio, the following conditions matter: - Tracking post history with version control...
Other Project
Other ProjectBuilding a Guessing Game System Based on Human-Robot Interaction
I helped develop a guessing game system based on human-robot interaction that combines YOLO object detection with a VLM (vision-language model). We built a game in which the robot arm infers and points to an object from the user's clues.
Other ProjectDesigning a Rectilinear Steiner Tree Algorithm for VLSI Routing
I implemented a Dijkstra-based Rectilinear Steiner Minimum Tree (RSMT) algorithm for routing optimization in VLSI design. It minimizes total wirelength by selecting Steiner candidate points from the Hanan grid and optimizing iteratively.
Other ProjectDC Motor Position Controller: Meeting Settling Time with PID and Root Locus
I designed a position controller for a DC servo motor in MATLAB. Under the requirements of a damping ratio of 0.4–0.7, a settling time under 1/30 s, and a phase margin of at least 40 degrees, I found the PID gains with the root locus, checked that the requirements were met and searched for the optimum, and wrote up my reflections.
Other ProjectPower Generation and Transmission Planning: Objectives and Constraints
A generation and transmission planning project from a power systems engineering course. It models new power plants and transmission expansion to meet long-term demand growth as a cost-minimization problem, and covers the constraints, power flow calculation, MILP optimization, and scenario analysis.