SoC Note
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SoC NoteARM Cortex-M0 Architecture: Register Set, Operating Modes, Memory Map
Notes on the Cortex-M0, an ARMv6-M core for ultra-low-power MCUs. Covers its features and structure, register set, operating modes, memory map, exceptions and interrupts, the Thumb instruction set, the 3-stage pipeline, SysTick, and a comparison with the Cortex-M3 and M4.
SoC NoteSoC Design Frameworks and the Design Productivity Gap
Notes on the SoC design flow. Covers the design productivity gap, where design productivity fails to keep up with process advances, and its remedies (abstraction, EDA automation, IP reuse), an ARM-based SoC example, a comparison of SoC, MCU, and CPU, and Apple SoCs with their die sizes.
SoC NoteSoC Programming in C: Controlling Memory-Mapped I/O Registers
Notes on programming an SoC in C. Covers memory-mapped I/O and volatile, struct-based register access, setting, clearing, toggling, and checking bits, multi-bit fields, the startup sequence, linker scripts, CMSIS, and interrupt handlers.
SoC NoteClassifying the ARM Thumb Instruction Set: Data Processing Instructions
Notes classifying the Cortex-M0 Thumb instruction set by type. Covers the syntax and encoding of register, immediate, logical, shift, and multiply data processing instructions; basic, offset, multiple, and PC-relative loads and stores; and branch instructions.
SoC NoteAMBA 3 AHB-Lite Bus Architecture: Signals and Transaction Behavior
Notes on AMBA 3 AHB-Lite, the standard system bus for Cortex-M0 and M3. Covers the single-master structure, master and slave signals, pipelined transactions and wait states, burst transfers and HTRANS, address decoding, and the AHB-APB bridge.
SoC NoteProcessor vs. Core: Instruction Stages and Layers of Abstraction
Notes on processor concepts and design. Covers the instruction processing stages, the abstraction layers from high-level languages down to machine code, the difference between a core and a processor, the processor design flow, the ARM Cortex family, design trade-offs, and a walkthrough of executing an ADD instruction.
SoC NoteComparing Chip Design Methodologies: Full-Custom, Standard-Cell, PLD
Notes on the semiconductor circuit design process and SoC design methodologies. Covers the steps from specification through layout, verification, and fabrication, a comparison of full-custom, standard-cell, and PLD approaches, and integrating internal vs. external IP and hard vs. soft IP.
SoC NoteCortex-M NVIC Interrupt Handling: Vector Table and Exception Priority
Notes on interrupt handling in the Cortex-M. Covers the difference between interrupts and exceptions, vectored and nested interrupts in the NVIC, the vector table and handling sequence, exception priority and preemption, tail-chaining and late arrival, and PRIMASK, FAULTMASK, and BASEPRI masking.