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Embedded NoteIntro to ARM Embedded Systems: ARM vs. Thumb Instruction Sets
Notes from an introduction to ARM embedded systems. Covers what an embedded system is and why ARM is used there, and compares the data sizes and characteristics of the 16-bit Thumb instructions introduced in ARMv4 with the 32-bit ARM instructions.
SoC NoteARM Cortex-M0 Architecture: Register Set, Operating Modes, Memory Map
Notes on the Cortex-M0, an ARMv6-M core for ultra-low-power MCUs. Covers its features and structure, register set, operating modes, memory map, exceptions and interrupts, the Thumb instruction set, the 3-stage pipeline, SysTick, and a comparison with the Cortex-M3 and M4.
SoC NoteSoC Design Frameworks and the Design Productivity Gap
Notes on the SoC design flow. Covers the design productivity gap, where design productivity fails to keep up with process advances, and its remedies (abstraction, EDA automation, IP reuse), an ARM-based SoC example, a comparison of SoC, MCU, and CPU, and Apple SoCs with their die sizes.
SoC NoteSoC Programming in C: Controlling Memory-Mapped I/O Registers
Notes on programming an SoC in C. Covers memory-mapped I/O and volatile, struct-based register access, setting, clearing, toggling, and checking bits, multi-bit fields, the startup sequence, linker scripts, CMSIS, and interrupt handlers.
SoC NoteClassifying the ARM Thumb Instruction Set: Data Processing Instructions
Notes classifying the Cortex-M0 Thumb instruction set by type. Covers the syntax and encoding of register, immediate, logical, shift, and multiply data processing instructions; basic, offset, multiple, and PC-relative loads and stores; and branch instructions.
SoC NoteAMBA 3 AHB-Lite Bus Architecture: Signals and Transaction Behavior
Notes on AMBA 3 AHB-Lite, the standard system bus for Cortex-M0 and M3. Covers the single-master structure, master and slave signals, pipelined transactions and wait states, burst transfers and HTRANS, address decoding, and the AHB-APB bridge.
SoC NoteProcessor vs. Core: Instruction Stages and Layers of Abstraction
Notes on processor concepts and design. Covers the instruction processing stages, the abstraction layers from high-level languages down to machine code, the difference between a core and a processor, the processor design flow, the ARM Cortex family, design trade-offs, and a walkthrough of executing an ADD instruction.
SoC NoteComparing Chip Design Methodologies: Full-Custom, Standard-Cell, PLD
Notes on the semiconductor circuit design process and SoC design methodologies. Covers the steps from specification through layout, verification, and fabrication, a comparison of full-custom, standard-cell, and PLD approaches, and integrating internal vs. external IP and hard vs. soft IP.
SoC NoteCortex-M NVIC Interrupt Handling: Vector Table and Exception Priority
Notes on interrupt handling in the Cortex-M. Covers the difference between interrupts and exceptions, vectored and nested interrupts in the NVIC, the vector table and handling sequence, exception priority and preemption, tail-chaining and late arrival, and PRIMASK, FAULTMASK, and BASEPRI masking.
Microprocessor NoteCrossbar Bus Architecture: From Shared Bus to Full Matrix
Notes on the crossbar bus that connects multiple masters and slaves. Covers the evolution from shared bus to hierarchical bus to full matrix, the PL301 structure and arbitration schemes, pipelined and burst transfers, QoS, scaling to NoC, and clock domain crossing.
Microprocessor NoteAMBA APB Protocol: Signals and Read/Write Transfer Timing
Notes on the AMBA 3 APB protocol. Covers the characteristics and signals of this bus for low-speed peripherals, read and write transfer timing with and without wait states, the APB slave state machine, the AHB-APB bridge, and a comparison of APB and AHB.
Microprocessor NoteDigital Adder Design: Half/Full Adders and Ripple Carry Adder Delay
Notes on digital adder architectures. Covers half and full adders with propagate and generate, transistor-level design, and ripple carry adder delay, through carry lookahead, carry skip and carry select, and Brent-Kung and Kogge-Stone adders.
Microprocessor NoteHow CMOS Transistors Work: From the PN Junction to nMOS/pMOS
Notes on CMOS fundamentals. Covers ICs and VLSI, silicon and the PN junction, nMOS and pMOS transistor operation and the switch model, the CMOS inverter and compound gates such as NAND and NOR, why CMOS saves power, and the process cross-section.
Microprocessor NoteDatapath Functional Units: Barrel Shifters, Comparators, Multipliers
Notes on the functional units of a processor datapath. Covers the structure and area/delay characteristics of barrel shifters, equality and magnitude comparators, array multipliers and Booth encoding, Wallace and Dadda trees, and restoring and non-restoring dividers.
Computer Architecture NoteComputer Architecture Basics: ISA, Abstraction Layers, and Performance
Notes on the introduction to a computer architecture course. Covers abstract data types (ADTs) with a stack example, the instruction set architecture (ISA), Hennessy and Patterson's engineering methodology and its two golden rules, and performance evaluation methods and design techniques.
Computer Architecture NoteHow Virtual Memory Works: Paging and Virtual-to-Physical Translation
Notes on how virtual memory works. Covers paging, which splits the virtual address space into pages, translation from virtual to physical addresses, page table organization and the PTBR, the TLB, and the pros and cons of demand paging.
Computer Architecture NoteMemory Hierarchy and Caches: The Memory Wall and Four Cache Design Questions
Notes on the memory hierarchy and caches. Covers the memory wall and temporal and spatial locality, hierarchy terminology, the four questions of cache design (placement, identification, replacement, writes), a direct-mapped cache example, and how block size relates to miss rate.
Computer Architecture NotePipelining and Hazards: Analyzing the 5-Stage MIPS Pipeline
Notes on pipelining principles using the 5-stage MIPS pipeline. Covers a performance comparison with sequential execution, structural, data, and control hazards with stalls and bubbles, the load-use hazard, a worked CPI example, and superpipelining and superscalar designs.
Computer Architecture NoteMultiprocessors and Shared-Memory Sync: Critical Sections, Producer-Consumer
Notes on multiprocessor architecture. Covers UMA and NUMA shared memory, a sum reduction example, the producer-consumer and critical-section problems, Test-and-Set mutual exclusion and optimized synchronization, message passing and clusters, and interconnect structures.
Computer Architecture NoteStorage and I/O System Architecture: I/O Buses and Reliability (MTTF)
Notes on computer I/O systems. Covers I/O bus connections and per-device data rates, the reliability metrics MTTF and MTTR and how to improve them, I/O register mapping, polling and interrupts and how they differ from exceptions, DMA, and RAID configurations.
Embedded NoteInside the ARM Processor: The 3-Stage Pipeline and Instruction Execution
Notes on the organization and implementation of ARM processors. Covers the main components such as the register file, barrel shifter, and ALU, the 3-stage pipeline, the memory bottleneck, the evolution to the 5-stage ARM9, data forwarding, and multiple load/store.
Embedded NoteRaspberry Pi Hardware: The Cache Hierarchy and ARM vs x86
Notes on Raspberry Pi hardware. Covers the BCM2711 SoC specs, L1 and L2 cache organization and associativity, ARM vs x86, Windows vs Linux, and Linux basics such as shell commands, file commands, pipes, and redirection.
Embedded NoteIntro to Raspberry Pi Hardware Hacking: GPIO, UART, I2C, and SPI
Introductory notes on hardware hacking: driving external devices directly from a Raspberry Pi. Covers how the GPIO, UART, I2C, and SPI buses work and where they fall short, controlling an LED circuit with wiringPi, and hands-on manipulation of the BCM2835 peripheral registers.
Embedded NoteInside the ARM Cortex-M3: Harvard Architecture, Registers, and xPSR
Notes on the structure of the ARMv7-M-based Cortex-M3. Covers its specifications, modified Harvard memory architecture, 3-stage pipeline, general-purpose registers R0~R12, the APSR, IPSR, and EPSR flags in xPSR, and the PRIMASK, FAULTMASK, and BASEPRI special registers.
Embedded NoteARM Assembly Basics: Instruction Format and Arithmetic/Logic Operations
Notes on the basics of ARM assembly programming. Covers instruction format and suffixes, arithmetic, logical, shift, and comparison operations, immediate value rules, shifted register operands, setting condition codes, addressing modes, and branches and subroutines, with examples.
Embedded NoteARM Architecture and Registers: Banked Registers by Processor Mode
Notes on the programmer's model of the ARM architecture. Covers the version lineage, visible registers, banked registers by processor mode, the PC and CPSR, supervisor mode, the load-store architecture, and data processing and control flow instructions.