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RISC-VRISC-V Branches and Jumps: Resolve Stage, JAL/JALR, Return-Address Stack Hints
Part 18 of the RISC-V series. I added the branch resolve stage, JAL redirect in ID, BTFN static prediction, and a RAS that follows the hints in spec section 2.5 to a pipeline model and compared them. CPI dropped from 1.368 to 1.227, and an 8-entry RAS predicted 98.3% of fib's returns.
RISC-VRISC-V 5-Stage Pipeline: Forwarding and Stall Conditions, Handling x0
Part 17 of the RISC-V series. I ran the same programs on a 5-stage pipeline model, matched them against QEMU, and measured CPI: 1.37 with forwarding, 1.83 without. Dropping the rd≠0 condition made a program using the HINT ntl.all write 0x80000000 instead of 0.
RISC-VThe Immediate Generator and a RISC-V Single-Cycle Datapath
Part 16 of the RISC-V series. I turned the selector table from Part 2 into an immediate generator circuit and assembled a single-cycle datapath. Running 5 programs and 1,076,364 instructions matched QEMU on every pc trace and register, and 20.0% of instructions were branches (58.5% of them taken).
RISC-VRISC-V Decoder Design: Decode Tables, Formats, and Illegal Instructions
Part 15 of the RISC-V series. Fills in the RV32I decode table down to the control signals and defines five illegal instruction conditions, then checks it against GNU objdump on 174,608 words. 165,923 matched, and all 8,685 mismatches were explained by four causes.
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Embedded NoteARM Architecture and Registers: Banked Registers by Processor Mode
Notes on the programmer's model of the ARM architecture. Covers the version lineage, visible registers, banked registers by processor mode, the PC and CPSR, supervisor mode, the load-store architecture, and data processing and control flow instructions.
Embedded NoteIntro to ARM Embedded Systems: ARM vs. Thumb Instruction Sets
Notes from an introduction to ARM embedded systems. Covers what an embedded system is and why ARM is used there, and compares the data sizes and characteristics of the 16-bit Thumb instructions introduced in ARMv4 with the 32-bit ARM instructions.
SoC NoteComparing Chip Design Methodologies: Full-Custom, Standard-Cell, PLD
Notes on the semiconductor circuit design process and SoC design methodologies. Covers the steps from specification through layout, verification, and fabrication, a comparison of full-custom, standard-cell, and PLD approaches, and integrating internal vs. external IP and hard vs. soft IP.
Embedded NoteARM Assembly Basics: Instruction Format and Arithmetic/Logic Operations
Notes on the basics of ARM assembly programming. Covers instruction format and suffixes, arithmetic, logical, shift, and comparison operations, immediate value rules, shifted register operands, setting condition codes, addressing modes, and branches and subroutines, with examples.
Popular projects
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AI ProjectImplementing Deep RL Algorithms: Comparing DQN, Double DQN, and PER
Compares three reinforcement learning algorithms, DQN, Double DQN, and PER, in the CartPole, Acrobot, and MountainCar environments, and analyzes the characteristics and limits of each.
Hardware ProjectZynq-7000 FPGA AI Accelerator: CNN/FC Cores and AXI CDMA Data Movement
I built an AI accelerator on a Zynq-7000 FPGA by designing CNN and fully connected compute cores and an AXI CDMA data mover. This post covers the Vivado and Vitis work: the design flow, the memory map, verifying the cores and movers, and building a 5-stage AI model.
Hardware ProjectBuilding an Arduino Auto Fire Extinguisher: Flame, Smoke, Heat Sensing + IoT
KURUNG, an Arduino auto fire extinguisher entered in Sungkyunkwan University's 2021 Creative Capstone Design Competition. We built a low-cost IoT device that judges flame, smoke, and temperature sensors together to detect kitchen fires early, sprays extinguishing agent, and alerts a smartphone.
Hardware ProjectAn 8-Bit Breadboard Computer Built from 74LS Chips: How a CPU Works
Following Ben Eater's design, I built an 8-bit computer on breadboards using only 74LS-series TTL chips. A record of learning the CPU's instruction execution cycle by wiring the clock, registers, ALU, RAM, program counter, and control unit by hand.