F and D Extensions: FP Registers, Rounding, fcsr Flags, NaN Boxing
Part 10 of the RISC-V series. I ran 229 instructions on QEMU covering the F and D extensions' rounding modes and exception flags, the canonical NaN, NaN boxing, and saturation rules for out-of-range integer conversion, and confirmed that all of them matched an exact-fraction reference model.
Sunhong'sSystem Blog
RISC-V