RISC-V Decoder Design: Decode Tables, Formats, and Illegal Instructions
Part 15 of the RISC-V series. Fills in the RV32I decode table down to the control signals and defines five illegal instruction conditions, then checks it against GNU objdump on 174,608 words. 165,923 matched, and all 8,685 mismatches were explained by four causes.
Sunhong'sSystem Blog
RISC-V