Posts / Tag
#lr/sc
2 posts
RISC-VThe A Extension: LR/SC, AMOs, and aq/rl
Part 8 of the RISC-V series. I checked the A extension's LR/SC reservations and failure conditions, the nine AMOs, and the aq/rl bits on QEMU. With 8 harts racing on a counter, plain increments kept only 22% while every atomic method was exact, and I found that QEMU lets sc succeed after another hart re-stores the same value.
RISC-VImplementing the A Extension: Reservations, Where AMOs Run, aq/rl, FENCE
Part 20 of the RISC-V series. I compared LR/SC reservation sets, AMO atomicity, and aq/rl and FENCE implementations with a two-hart model. If reservations aren't cleared on another hart's store, the counter drops to 69.6%, and QEMU let SC succeed in all 20 runs of an ABA test.