Posts / Tag
#rvv
2 posts
RISC-VV Extension 2: Masks, Load/Store Types, Reductions, Permutes, Tail/Mask Agnostic
Part 14 of the RISC-V series. I ran v0 masks, the four kinds of loads and stores, a first-fault strlen, reductions and permutations, and ta/ma in QEMU. Four kernels matched Python on all 78 items, and at VLEN 1024 they executed 4–7% as many instructions as scalar code.
RISC-VV Extension 1: VLEN, SEW, LMUL, vsetvli, and Vector-Length-Agnostic Code
Part 13 of the RISC-V series. Covers vector registers, VLEN, SEW, and LMUL, and the rules by which vsetvli sets vl. Running the same machine code on QEMU at VLEN 128 to 1024, a 100-element add looped 25, 13, 7, and 4 times and executed 313 to 61 instructions (813 for scalar).