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#decoder
2 posts
RISC-VRISC-V Decoder Design: Decode Tables, Formats, and Illegal Instructions
Part 15 of the RISC-V series. Fills in the RV32I decode table down to the control signals and defines five illegal instruction conditions, then checks it against GNU objdump on 174,608 words. 165,923 matched, and all 8,685 mismatches were explained by four causes.
RISC-VRV32I 1: Registers, Six Instruction Formats, and Why Immediates Are Scrambled
Part 2 of the RISC-V series. Looks at RV32I's registers and six instruction formats, and explains why the immediate bits are scrambled by counting multiplexer inputs in the immediate generator (70 vs. 98). A hand-written encoder and decoder were checked against GNU as on 5,000 instructions.