Posts / Tag
#rv32i
4 posts
RISC-VRISC-V Decoder Design: Decode Tables, Formats, and Illegal Instructions
Part 15 of the RISC-V series. Fills in the RV32I decode table down to the control signals and defines five illegal instruction conditions, then checks it against GNU objdump on 174,608 words. 165,923 matched, and all 8,685 mismatches were explained by four causes.
RISC-VRV32I 3: Branches, Jumps, Loads/Stores and Alignment, FENCE, ECALL/EBREAK
Part 4 of the RISC-V series. I ran the six branches, jal/jalr, load sign extension, misaligned accesses, and fence/ecall/ebreak on QEMU. jalr turned 0x80000021 into 0x80000020, and all 56 results matched a reference model.
RISC-VRV32I 2: Integer Ops, Compares, Shifts, and Building Constants with lui/auipc
Part 3 of the RISC-V series. Checks RV32I integer arithmetic, compares, shifts, and flagless overflow handling on QEMU with 15 edge cases, then examines the +1 correction for building 32-bit constants and addresses with lui and auipc through 1 million random trials.
RISC-VRV32I 1: Registers, Six Instruction Formats, and Why Immediates Are Scrambled
Part 2 of the RISC-V series. Looks at RV32I's registers and six instruction formats, and explains why the immediate bits are scrambled by counting multiplexer inputs in the immediate generator (70 vs. 98). A hand-written encoder and decoder were checked against GNU as on 5,000 instructions.