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RISC-V
Nov 4, 2026

RV64I: W Instructions, Sign-Extension Rules, and What Differs from 32-Bit

Part 5 of the RISC-V series. I checked RV64I's W instructions and sign-extension rules on QEMU. 0x7fffffff+1 became 0xffffffff80000000 with addw, and 64-bit constants took an average of 7.887 instructions with li. I also look at why utoa10 from part 1 grew.