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#qemu
11 posts
RISC-VThe Immediate Generator and a RISC-V Single-Cycle Datapath
Part 16 of the RISC-V series. I turned the selector table from Part 2 into an immediate generator circuit and assembled a single-cycle datapath. Running 5 programs and 1,076,364 instructions matched QEMU on every pc trace and register, and 20.0% of instructions were branches (58.5% of them taken).
RISC-VThe A Extension: LR/SC, AMOs, and aq/rl
Part 8 of the RISC-V series. I checked the A extension's LR/SC reservations and failure conditions, the nine AMOs, and the aq/rl bits on QEMU. With 8 harts racing on a counter, plain increments kept only 22% while every atomic method was exact, and I found that QEMU lets sc succeed after another hart re-stores the same value.
RISC-VThe M Extension: Multiply, Divide, and the Rules for Divide-by-Zero and Overflow
Part 7 of the RISC-V series. Covers the 13 multiply and divide instructions of the M extension and the defined results for divide-by-zero and overflow (no exceptions), then runs 1,948 boundary cases on QEMU and confirms they all match a reference model. Without M, each multiply costs 86 extra instructions.
RISC-VFENCE.I and Self-Modifying Code: What the Instruction Side Must Honor
Part 22 of the RISC-V series. Covers FENCE.I and self-modifying code. Without fence.i, QEMU ran the new code when it was written elsewhere but the old code inside the block being executed. Running 16 combinations on an instruction-set model, I identified the minimal FENCE.I implementation for each core organization.
RISC-VImplementing the A Extension: Reservations, Where AMOs Run, aq/rl, FENCE
Part 20 of the RISC-V series. I compared LR/SC reservation sets, AMO atomicity, and aq/rl and FENCE implementations with a two-hart model. If reservations aren't cleared on another hart's store, the counter drops to 69.6%, and QEMU let SC succeed in all 20 runs of an ABA test.
RISC-VF and D Extensions: FP Registers, Rounding, fcsr Flags, NaN Boxing
Part 10 of the RISC-V series. I ran 229 instructions on QEMU covering the F and D extensions' rounding modes and exception flags, the canonical NaN, NaN boxing, and saturation rules for out-of-range integer conversion, and confirmed that all of them matched an exact-fraction reference model.
RISC-VV Extension 2: Masks, Load/Store Types, Reductions, Permutes, Tail/Mask Agnostic
Part 14 of the RISC-V series. I ran v0 masks, the four kinds of loads and stores, a first-fault strlen, reductions and permutations, and ta/ma in QEMU. Four kernels matched Python on all 78 items, and at VLEN 1024 they executed 4–7% as many instructions as scalar code.
RISC-VV Extension 1: VLEN, SEW, LMUL, vsetvli, and Vector-Length-Agnostic Code
Part 13 of the RISC-V series. Covers vector registers, VLEN, SEW, and LMUL, and the rules by which vsetvli sets vl. Running the same machine code on QEMU at VLEN 128 to 1024, a 100-element add looped 25, 13, 7, and 4 times and executed 313 to 61 instructions (813 for scalar).
RISC-VRV64I: W Instructions, Sign-Extension Rules, and What Differs from 32-Bit
Part 5 of the RISC-V series. I checked RV64I's W instructions and sign-extension rules on QEMU. 0x7fffffff+1 became 0xffffffff80000000 with addw, and 64-bit constants took an average of 7.887 instructions with li. I also look at why utoa10 from part 1 grew.
RISC-VRV32I 3: Branches, Jumps, Loads/Stores and Alignment, FENCE, ECALL/EBREAK
Part 4 of the RISC-V series. I ran the six branches, jal/jalr, load sign extension, misaligned accesses, and fence/ecall/ebreak on QEMU. jalr turned 0x80000021 into 0x80000020, and all 56 results matched a reference model.
RISC-VRV32I 2: Integer Ops, Compares, Shifts, and Building Constants with lui/auipc
Part 3 of the RISC-V series. Checks RV32I integer arithmetic, compares, shifts, and flagless overflow handling on QEMU with 15 edge cases, then examines the +1 correction for building 32-bit constants and addresses with lui and auipc through 1 million random trials.