Posts / Tag

#C

2 posts

Hardware Project

Dec 13, 2023

A 5-Stage Pipelined RISC-V Processor in Verilog: Hazards and Forwarding

I designed a 5-stage pipelined RISC-V processor in Verilog that supports the full RV32I instruction set. This post covers resolving data and control hazards with a hazard detection unit and a forwarding unit, and verifying the design with iverilog and GTKWave waveforms.

Hardware Project

Dec 8, 2023

Zynq-7000 FPGA AI Accelerator: CNN/FC Cores and AXI CDMA Data Movement

I built an AI accelerator on a Zynq-7000 FPGA by designing CNN and fully connected compute cores and an AXI CDMA data mover. This post covers the Vivado and Vitis work: the design flow, the memory map, verifying the cores and movers, and building a 5-stage AI model.