#verilog

8 posts

Dec 27, 2023

Radix-8 Booth Multiplier: Encoding Table and TDM Trade-offs (Verilog)

I designed a multiplier in Verilog that combines Radix-8 Booth encoding with TDM. This post covers how the Booth algorithm works, the number of partial products and hardware trade-offs at each radix, the Radix-8 encoding table, implementation and verification, and lessons learned.

Dec 27, 2023

Radix-4 Booth Multiplier: Partial Product Reduction with TDM (Verilog)

I designed a radix-4 multiplier in Verilog that cuts the number of partial products with Booth encoding and compresses them with TDM. Covers the Booth encoder and selector, partial product generation, the carry save adder, the Kogge-Stone final adder, and the accuracy verification waveforms.

Dec 27, 2023

Cortex-M0 SoC Design: A Multifunction Robot Control System on AHB-Lite

Designed an SoC on a Basys3 board that combines a Cortex-M0 with AHB-Lite peripherals. Covers the HW and SW of a multifunction system that controls a small robot over UART and runs an up counter, a stopwatch, a random number generator/multiplier, and an adder/subtractor, along with the results.

Dec 13, 2023

Designing a Verilog Slot Machine: LFSR Random Numbers and a Timer Seed (Basys3)

I designed a slot machine for the Basys3 board in Verilog. A timer seeds an LFSR to produce three BCD random numbers, and the output is 2x, 5x, or 10x the input depending on how many digits match. Covers the block diagram, sub-block definitions, simulation waveforms, and discussion.

Dec 13, 2023

Wallace Tree Multiplier in Verilog: 8-Bit Parallel Multiply with Adders

I designed an 8-bit parallel multiplier in Verilog using the Wallace tree structure, which reduces partial sums stage by stage with half adders and full adders. Covers the computation that produces the 16-bit product, the design flow, the testbench, and the full code.

Dec 13, 2023

A 5-Stage Pipelined RISC-V Processor in Verilog: Hazards and Forwarding

I designed a 5-stage pipelined RISC-V processor in Verilog that supports the full RV32I instruction set. This post covers resolving data and control hazards with a hazard detection unit and a forwarding unit, and verifying the design with iverilog and GTKWave waveforms.

Dec 8, 2023

Zynq-7000 FPGA AI Accelerator: CNN/FC Cores and AXI CDMA Data Movement

I built an AI accelerator on a Zynq-7000 FPGA by designing CNN and fully connected compute cores and an AXI CDMA data mover. This post covers the Vivado and Vitis work: the design flow, the memory map, verifying the cores and movers, and building a 5-stage AI model.

Jan 6, 2023

Kogge-Stone Adder in Verilog: Fewer Logic Levels with Higher-Valency Cells

I designed a Kogge-Stone adder, the tree adder with the fewest logic levels, in Verilog using higher-valency cells. Covers the bitwise PG, group PG, and SUM logic code, testbench waveform verification, and the performance optimizations and analysis.